From: Julian Seward Date: Fri, 4 Nov 2005 14:34:52 +0000 (+0000) Subject: Handle jecxz in addition to jrcxz. X-Git-Tag: svn/VALGRIND_3_1_1^2~58 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a689fb4debf4e494ec27d8425e3a896f5662c898;p=thirdparty%2Fvalgrind.git Handle jecxz in addition to jrcxz. git-svn-id: svn://svn.valgrind.org/vex/trunk@1433 --- diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c index c3facac114..effe68244c 100644 --- a/VEX/priv/guest-amd64/toIR.c +++ b/VEX/priv/guest-amd64/toIR.c @@ -11635,19 +11635,30 @@ DisResult disInstr_AMD64_WRK ( DIP("j%s-8 0x%llx\n", name_AMD64Condcode(opc - 0x70), d64); break; - case 0xE3: /* JRCXZ or perhaps JECXZ, depending on OSO ? Intel - manual says it depends on address size override, - which doesn't sound right to me. But the amd manual - alsay says that, so I guess it is. In which case 8 - is the only valid size. */ - if (have66orF2orF3(pfx) || haveASO(pfx)) goto decode_failure; + case 0xE3: + /* JRCXZ or JECXZ, depending address size override. */ + if (have66orF2orF3(pfx)) goto decode_failure; d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta); delta++; - stmt( IRStmt_Exit( binop(Iop_CmpEQ64, getIReg64(R_RCX), mkU64(0)), - Ijk_Boring, - IRConst_U64(d64)) - ); - DIP("jrcxz 0x%llx\n", d64); + if (haveASO(pfx)) { + /* 32-bit */ + stmt( IRStmt_Exit( binop(Iop_CmpEQ64, + unop(Iop_32Uto64, getIReg32(R_RCX)), + mkU64(0)), + Ijk_Boring, + IRConst_U64(d64)) + ); + DIP("jecxz 0x%llx\n", d64); + } else { + /* 64-bit */ + stmt( IRStmt_Exit( binop(Iop_CmpEQ64, + getIReg64(R_RCX), + mkU64(0)), + Ijk_Boring, + IRConst_U64(d64)) + ); + DIP("jrcxz 0x%llx\n", d64); + } break; case 0xE0: /* LOOPNE disp8: decrement count, jump if count != 0 && ZF==0 */