From: Greg Kroah-Hartman Date: Tue, 16 Jun 2026 10:14:11 +0000 (+0530) Subject: 7.0-stable patches X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=a8379c0dc85f4df89f63f91c68a4f7b99d37952e;p=thirdparty%2Fkernel%2Fstable-queue.git 7.0-stable patches added patches: arm64-cputype-add-c1-premium-definitions.patch arm64-cputype-add-c1-ultra-definitions.patch --- diff --git a/queue-7.0/arm64-cputype-add-c1-premium-definitions.patch b/queue-7.0/arm64-cputype-add-c1-premium-definitions.patch new file mode 100644 index 0000000000..0f9b6cf125 --- /dev/null +++ b/queue-7.0/arm64-cputype-add-c1-premium-definitions.patch @@ -0,0 +1,45 @@ +From d28413bfc5a255957241f1df5d7fd0c2cd74fe18 Mon Sep 17 00:00:00 2001 +From: Mark Rutland +Date: Tue, 9 Jun 2026 11:12:02 +0100 +Subject: arm64: cputype: Add C1-Premium definitions + +From: Mark Rutland + +commit d28413bfc5a255957241f1df5d7fd0c2cd74fe18 upstream. + +Add cputype definitions for C1-Premium. These will be used for errata +detection in subsequent patches. + +These values can be found in the C1-Premium TRM: + + https://developer.arm.com/documentation/109416/0100/ + +... in section A.5.1 ("MIDR_EL1, Main ID Register"). + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: Will Deacon +Signed-off-by: Will Deacon +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -99,6 +99,7 @@ + #define ARM_CPU_PART_CORTEX_A720AE 0xD89 + #define ARM_CPU_PART_C1_ULTRA 0xD8C + #define ARM_CPU_PART_NEOVERSE_N3 0xD8E ++#define ARM_CPU_PART_C1_PREMIUM 0xD90 + + #define APM_CPU_PART_XGENE 0x000 + #define APM_CPU_VAR_POTENZA 0x00 +@@ -191,6 +192,7 @@ + #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) + #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA) + #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) ++#define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) diff --git a/queue-7.0/arm64-cputype-add-c1-ultra-definitions.patch b/queue-7.0/arm64-cputype-add-c1-ultra-definitions.patch new file mode 100644 index 0000000000..ea00adae12 --- /dev/null +++ b/queue-7.0/arm64-cputype-add-c1-ultra-definitions.patch @@ -0,0 +1,45 @@ +From 60349e64a6c65f9f0aa118af711b3c7e137f07ff Mon Sep 17 00:00:00 2001 +From: Mark Rutland +Date: Tue, 9 Jun 2026 11:12:01 +0100 +Subject: arm64: cputype: Add C1-Ultra definitions + +From: Mark Rutland + +commit 60349e64a6c65f9f0aa118af711b3c7e137f07ff upstream. + +Add cputype definitions for C1-Ultra. These will be used for errata +detection in subsequent patches. + +These values can be found in the C1-Ultra TRM: + + https://developer.arm.com/documentation/108014/0100/ + +... in section A.5.1 ("MIDR_EL1, Main ID Register"). + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: Will Deacon +Signed-off-by: Will Deacon +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -97,6 +97,7 @@ + #define ARM_CPU_PART_CORTEX_X925 0xD85 + #define ARM_CPU_PART_CORTEX_A725 0xD87 + #define ARM_CPU_PART_CORTEX_A720AE 0xD89 ++#define ARM_CPU_PART_C1_ULTRA 0xD8C + #define ARM_CPU_PART_NEOVERSE_N3 0xD8E + + #define APM_CPU_PART_XGENE 0x000 +@@ -188,6 +189,7 @@ + #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) + #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) + #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) ++#define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA) + #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) diff --git a/queue-7.0/series b/queue-7.0/series index 88600d7df4..113339f5d4 100644 --- a/queue-7.0/series +++ b/queue-7.0/series @@ -371,3 +371,5 @@ vsock-virtio-fix-potential-unbounded-skb-queue.patch vsock-virtio-fix-skb-overhead-accounting-to-preserve-full-buf_alloc.patch debugobjects-do-not-fill_pool-if-pi_blocked_on.patch debugobjects-don-t-call-fill_pool-in-early-boot-hardirq-context.patch +arm64-cputype-add-c1-ultra-definitions.patch +arm64-cputype-add-c1-premium-definitions.patch