From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Wed, 9 Dec 2015 10:13:31 +0000 (+0530)
Subject: dts: zynq: cse_qspi: Modify zynq cse qspi dts file
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=aac02384335d78c572d26e7101f54e1023f71f01;p=thirdparty%2Fu-boot.git

dts: zynq: cse_qspi: Modify zynq cse qspi dts file

Modify the zynq cse qspi dts file  by removing
the unrequired devices from it. This change is
to reduce the size required for dtb blob to run
u-boot from OCM

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynq-cse-qspi.dts b/arch/arm/dts/zynq-cse-qspi.dts
index ef71da95c63..076ac417581 100644
--- a/arch/arm/dts/zynq-cse-qspi.dts
+++ b/arch/arm/dts/zynq-cse-qspi.dts
@@ -6,9 +6,112 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /dts-v1/;
-#include "zynq-7000.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	model = "Zynq CSE QSPI Board";
 	compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
+
+	aliases {
+		spi0 = &qspi;
+		serial0 = &uart1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0xFFFC0000 0x40000>;
+	};
+
+	amba: amba {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&intc>;
+		ranges;
+
+		intc: interrupt-controller@f8f01000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0xF8F01000 0x1000>,
+			      <0xF8F00100 0x100>;
+		};
+
+		qspi: spi@e000d000 {
+			clock-names = "ref_clk", "pclk";
+			clocks = <&clkc 10>, <&clkc 43>;
+			compatible = "xlnx,zynq-qspi-1.0";
+			status = "okay";
+			interrupt-parent = <&intc>;
+			interrupts = <0 19 4>;
+			reg = <0xe000d000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			is-dual = <0>;
+			num-cs = <1>;
+			flash@0 {
+				compatible = "n25q128a11";
+				reg = <0x0>;
+				spi-tx-bus-width = <1>;
+				spi-rx-bus-width = <4>;
+				spi-max-frequency = <50000000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				partition@qspi-fsbl-uboot {
+					label = "qspi-fsbl-uboot";
+					reg = <0x0 0x100000>;
+				};
+				partition@qspi-linux {
+					label = "qspi-linux";
+					reg = <0x100000 0x500000>;
+				};
+				partition@qspi-device-tree {
+					label = "qspi-device-tree";
+					reg = <0x600000 0x20000>;
+				};
+				partition@qspi-rootfs {
+					label = "qspi-rootfs";
+					reg = <0x620000 0x5E0000>;
+				};
+				partition@qspi-bitstream {
+					label = "qspi-bitstream";
+					reg = <0xC00000 0x400000>;
+				};
+			};
+		};
+
+		uart1: serial@e0001000 {
+			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
+			status = "okay";
+			clocks = <&clkc 24>, <&clkc 41>;
+			clock-names = "uart_clk", "pclk";
+			reg = <0xE0001000 0x1000>;
+			interrupts = <0 50 4>;
+		};
+
+		slcr: slcr@f8000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+			reg = <0xF8000000 0x1000>;
+			ranges;
+			clkc: clkc@100 {
+				#clock-cells = <1>;
+				compatible = "xlnx,ps7-clkc";
+				fclk-enable = <0xf>;
+				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
+						"gem1_aper", "sdio0_aper", "sdio1_aper",
+						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+						"dbg_trc", "dbg_apb";
+				reg = <0x100 0x100>;
+			};
+		};
+	};
 };