From: Michal Simek Date: Thu, 17 Oct 2013 15:07:08 +0000 (+0200) Subject: Merge tag 'v2013.10' into xilinx/master-next X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=ab16b5f0fbacf44b46c91884ee9cfd32e60dc4b3;p=thirdparty%2Fu-boot.git Merge tag 'v2013.10' into xilinx/master-next Fix several merge conflicts in spi subsystem. Also fix all SPDX licenses in our private code and our platforms in boards.cfg. I2C subsystem has changed that's why I have disabled CONFIG_SYS_I2C from zynq_common.h. Signed-off-by: Michal Simek --- ab16b5f0fbacf44b46c91884ee9cfd32e60dc4b3 diff --cc Makefile index 4218226e160,dc0417914e7..dc0417914e7 mode 100755,100644..100755 --- a/Makefile +++ b/Makefile diff --cc arch/arm/cpu/armv7/zynq/config.mk index 85996f3255f,00000000000..9f90a2e65be mode 100644,000000..100644 --- a/arch/arm/cpu/armv7/zynq/config.mk +++ b/arch/arm/cpu/armv7/zynq/config.mk @@@ -1,25 -1,0 +1,8 @@@ +# - # (C) Copyright 2002 - # Gary Jennejohn, DENX Software Engineering, ++# Copyright (C) 2013 Xilinx, Inc. All rights reserved. +# - # See file CREDITS for list of people who contributed to this - # project. - # - # This program is free software; you can redistribute it and/or - # modify it under the terms of the GNU General Public License as - # published by the Free Software Foundation; either version 2 of - # the License, or (at your option) any later version. - # - # This program is distributed in the hope that it will be useful, - # but WITHOUT ANY WARRANTY; without even the implied warranty of - # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - # GNU General Public License for more details. - # - # You should have received a copy of the GNU General Public License - # along with this program; if not, write to the Free Software - # Foundation, Inc., 59 Temple Place, Suite 330, Boston, - # MA 02111-1307 USA ++# SPDX-License-Identifier: GPL-2.0+ +# +PLATFORM_RELFLAGS += -fno-strict-aliasing +# Xilinx, added to prevent unaligned accesses which started happening # with GCC 4.5.2 tools +PLATFORM_RELFLAGS += -mno-unaligned-access diff --cc arch/arm/cpu/armv7/zynq/lowlevel_init.S index d490eb5c9bb,00000000000..6d714b711cb mode 100644,000000..100644 --- a/arch/arm/cpu/armv7/zynq/lowlevel_init.S +++ b/arch/arm/cpu/armv7/zynq/lowlevel_init.S @@@ -1,42 -1,0 +1,26 @@@ +/* + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +ENTRY(lowlevel_init) + + /* Enable the the VFP */ + mrc p15, 0, r1, c1, c0, 2 + orr r1, r1, #(0x3 << 20) + orr r1, r1, #(0x3 << 20) + mcr p15, 0, r1, c1, c0, 2 + isb + fmrx r1, FPEXC + orr r1,r1, #(1<<30) + fmxr FPEXC, r1 + + /* Move back to caller */ + mov pc, lr + +ENDPROC(lowlevel_init) diff --cc arch/arm/lib/bootm.c index d27939d12e2,f476a897022..7d17b147205 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@@ -225,7 -230,11 +230,8 @@@ static void boot_prep_linux(bootm_heade } setup_board_tags(¶ms); setup_end_tag(gd->bd); - } else { - printf("FDT and ATAGS support not compiled in - hanging\n"); - hang(); } + do_nonsec_virt_switch(); } /* Subcommand: GO */ diff --cc boards.cfg index e84e5e19eb8,aa2ee642d41..fbb939301e1 --- a/boards.cfg +++ b/boards.cfg @@@ -26,1161 -26,1183 +26,1185 @@@ # #define CONFIG_HAS_BAR 1 # #define CONFIG_BAZ 64 # - # The list should be ordered according to the following fields, - # from most to least significant: - # - # ARCH, CPU, SoC, Vendor, Target - # - # To keep the list sorted, use something like - # :.,$! sort -bdf -k2,2 -k3,3 -k6,6 -k5,5 -k1,1 + # The maintainers field lists the e-mail addresses of the board's + # maintainers, separated by colons. NOTE: there are spaces in this field! + # For any board without permanent maintainer, please contact + # Wolfgang Denk + # And Cc: the mailing list. + + # The list should be ordered according to the C locale. # - # To reformat the list, use something like - # :.,$! column -t + # To keep the list formatted and sorted, script tools/reformat.py is available. + # It can be used from a shell: + # tools/reformat.py -i -d '-' -s 8 boards0.cfg && mv boards0.cfg boards.cfg + # It can directly be invoked from vim: + # :%!tools/reformat.py -i -d '-' -s 8 # - # Target ARCH CPU Board name Vendor SoC Options + # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers ########################################################################################################### - integratorcp_cm1136 arm arm1136 integrator armltd - integratorcp:CM1136 - imx31_phycore arm arm1136 - - mx31 - imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET - qong arm arm1136 - davedenx mx31 - mx31ads arm arm1136 - freescale mx31 - mx31pdk arm arm1136 - freescale mx31 - tt01 arm arm1136 - hale mx31 - imx31_litekit arm arm1136 - logicpd mx31 - flea3 arm arm1136 - CarMediaLab mx35 - mx35pdk arm arm1136 - freescale mx35 - woodburn arm arm1136 - - mx35 - woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg - tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x - rpi_b arm arm1176 rpi_b raspberrypi bcm2835 - integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T - integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T - integratorcp_cm920t arm arm920t integrator armltd - integratorcp:CM920T - a320evb arm arm920t - faraday a320 - at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek - at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT - eb_cpux9k2 arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2 - eb_cpux9k2_ram arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2:RAMBOOT - cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 - cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT - mx1ads arm arm920t - - imx - scb9328 arm arm920t - - imx - cm4008 arm arm920t - - ks8695 - cm41xx arm arm920t - - ks8695 - mini2440 arm arm920t mini2440 friendlyarm s3c24x0 - VCMA9 arm arm920t vcma9 mpl s3c24x0 - smdk2410 arm arm920t - samsung s3c24x0 - omap1510inn arm arm925t - ti - integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S - integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S - aspenite arm arm926ejs - Marvell armada100 - gplugd arm arm926ejs - Marvell armada100 - afeb9260 arm arm926ejs - - at91 - at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 - at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 - at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH - at91sam9261ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 - at91sam9261ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 - at91sam9261ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH - at91sam9263ek_dataflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH - at91sam9263ek_dataflash_cs0 arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH - at91sam9263ek_nandflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH - at91sam9263ek_norflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH - at91sam9263ek_norflash_boot arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH - at91sam9g10ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 - at91sam9g10ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 - at91sam9g10ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH - at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 - at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 - at91sam9g20ek_mmc arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_MMC - at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH - at91sam9g20ek_2mmc_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH - at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH - at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH - at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH - at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH - at91sam9x5ek_dataflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH - at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH - at91sam9x5ek_mmc arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC - at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 - at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 - at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH - at91sam9n12ek_nandflash arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH - at91sam9n12ek_spiflash arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH - at91sam9n12ek_mmc arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC - snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 - snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 - vl_ma2sc arm arm926ejs vl_ma2sc BuS at91 - vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD - sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM - sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH - tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM - tny_a9260_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH - tny_a9g20_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_EEPROM - tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH - ethernut5 arm arm926ejs ethernut5 egnite at91 ethernut5:AT91SAM9XE - top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000 - top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000 - meesc arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_NANDFLASH - meesc_dataflash arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_DATAFLASH - otc570 arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_NANDFLASH - otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH - cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 - cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M - cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT - cpu9260_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M,NANDBOOT - cpu9G20 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20 - cpu9G20_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M - cpu9G20_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,NANDBOOT - cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT - pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261 - pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263 - pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45 - portuxg20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20,PORTUXG20 - stamp9g20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20 - cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx - da830evm arm arm926ejs da8xxevm davinci davinci - da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 - da850evm arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH - da850evm_direct_nor arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT - davinci_dm355evm arm arm926ejs dm355evm davinci davinci - davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci - davinci_dm365evm arm arm926ejs dm365evm davinci davinci - davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:REFCLK_FREQ=27000000 - davinci_dm6467Tevm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 - davinci_dvevm arm arm926ejs dvevm davinci davinci - davinci_schmoogie arm arm926ejs schmoogie davinci davinci - davinci_sffsdr arm arm926ejs sffsdr davinci davinci - davinci_sonata arm arm926ejs sonata davinci davinci - ea20 arm arm926ejs ea20 davinci davinci - hawkboard arm arm926ejs da8xxevm davinci davinci - hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT - enbw_cmc arm arm926ejs enbw_cmc enbw davinci - calimain arm arm926ejs calimain omicron davinci - pogo_e02 arm arm926ejs - cloudengines kirkwood - dns325 arm arm926ejs - d-link kirkwood - iconnect arm arm926ejs - iomega kirkwood - lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 - lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL - km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD - km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI - kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA - kmsuv31 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_SUV31 - mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN - kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN - portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 - d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2 - inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 - net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 - netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2 - netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 - netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2 - netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 - wireless_space arm arm926ejs wireless_space LaCie kirkwood - dreamplug arm arm926ejs - Marvell kirkwood - guruplug arm arm926ejs - Marvell kirkwood - mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood - openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE - openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT - openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE - rd6281a arm arm926ejs - Marvell kirkwood - sheevaplug arm arm926ejs - Marvell kirkwood - ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood - dockstar arm arm926ejs - Seagate kirkwood - goflexhome arm arm926ejs - Seagate kirkwood - tk71 arm arm926ejs tk71 karo kirkwood - devkit3250 arm arm926ejs devkit3250 timll lpc32xx - jadecpu arm arm926ejs jadecpu syteco mb86r0x - mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg - tx25 arm arm926ejs tx25 karo mx25 - zmx25 arm arm926ejs zmx25 syteco mx25 - imx27lite arm arm926ejs imx27lite logicpd mx27 - magnesium arm arm926ejs imx27lite logicpd mx27 - mx23_olinuxino arm arm926ejs mx23_olinuxino olimex mxs mx23_olinuxino - apx4devkit arm arm926ejs apx4devkit bluegiga mxs apx4devkit - mx23evk arm arm926ejs mx23evk freescale mxs mx23evk - m28evk arm arm926ejs m28evk denx mxs m28evk - mx28evk arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_MMC - mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND - sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs - nhk8815 arm arm926ejs nhk8815 st nomadik - nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND - omap5912osk arm arm926ejs - ti omap - omap730p2 arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT - omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2:CS0_BOOT - omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT - edminiv2 arm arm926ejs - LaCie orion5x - dkb arm arm926ejs - Marvell pantheon - spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300 - spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand - spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty - spear300_usbtty_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty,nand - spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310 - spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR - spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand - spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty - spear310_usbtty_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,FLASH_PNOR - spear310_usbtty_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,nand - spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320 - spear320_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,FLASH_PNOR - spear320_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,nand - spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty - spear320_usbtty_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,FLASH_PNOR - spear320_usbtty_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,nand - spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600 - spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand - spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty - spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand - x600 arm arm926ejs - spear spear x600 - versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB - versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB - versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB - integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES - integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES - vexpress_ca15_tc2 arm armv7 vexpress armltd - vexpress_ca5x2 arm armv7 vexpress armltd - vexpress_ca9x4 arm armv7 vexpress armltd - am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 - am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT - am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 - am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 - am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 - am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 - am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 - am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT - ti814x_evm arm armv7 ti814x ti am33xx - pcm051 arm armv7 pcm051 phytec am33xx pcm051 - sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC - sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH - sama5d3xek_spiflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH - highbank arm armv7 highbank - highbank - m53evk arm armv7 m53evk denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg - mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg - mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg - mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg - mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg - mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg - ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg - cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q - mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg - mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q - mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg - mx6dlsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL - mx6qsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q - mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL - titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg - vf610twr arm armv7 vf610twr freescale vf610 vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg - eco5pk arm armv7 eco5pk 8dtech omap3 - nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 - nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 - nitrogen6q arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 - nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 - nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 - nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 - wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 - wandboard_quad arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 - wandboard_solo arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 - omap3_overo arm armv7 overo - omap3 - omap3_pandora arm armv7 pandora - omap3 - dig297 arm armv7 dig297 comelit omap3 - cm_t35 arm armv7 cm_t35 compulab omap3 - igep0020 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND - igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND - igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND - igep0033 arm armv7 igep0033 isee am33xx - am3517_evm arm armv7 am3517evm logicpd omap3 - mt_ventoux arm armv7 mt_ventoux teejet omap3 - omap3_zoom1 arm armv7 zoom1 logicpd omap3 - omap3_zoom2 arm armv7 zoom2 logicpd omap3 - omap3_logic arm armv7 omap3som logicpd omap3 - omap3_mvblx arm armv7 mvblx matrix_vision omap3 - am3517_crane arm armv7 am3517crane ti omap3 - omap3_beagle arm armv7 beagle ti omap3 - omap3_evm arm armv7 evm ti omap3 - omap3_evm_quick_mmc arm armv7 evm ti omap3 - omap3_evm_quick_nand arm armv7 evm ti omap3 - omap3_sdp3430 arm armv7 sdp3430 ti omap3 - devkit8000 arm armv7 devkit8000 timll omap3 - mcx arm armv7 mcx htkw omap3 - tricorder arm armv7 tricorder corscience omap3 - twister arm armv7 twister technexion omap3 - nokia_rx51 arm armv7 rx51 nokia omap3 - omap4_panda arm armv7 panda ti omap4 - omap4_sdp4430 arm armv7 sdp4430 ti omap4 - zynq_zc770_XM010 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM010 - zynq_zc770_XM011 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM011 - zynq_zc770_XM012 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM012 - zynq_zc770_XM013 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM013 - zynq_afx_nor arm armv7 zynq xilinx zynq zynq_afx:AFX_NOR - zynq_afx_qspi arm armv7 zynq xilinx zynq zynq_afx:AFX_QSPI - zynq_afx_nand arm armv7 zynq xilinx zynq zynq_afx:AFX_NAND - zynq_zc70x arm armv7 zynq xilinx zynq - zynq_zed arm armv7 zynq xilinx zynq - zynq_cse_qspi arm armv7 zynq xilinx zynq zynq_cse:CSE_QSPI - zynq_cse_nand arm armv7 zynq xilinx zynq zynq_cse:CSE_NAND - zynq_cse_nor arm armv7 zynq xilinx zynq zynq_cse:CSE_NOR - omap5_uevm arm armv7 omap5_uevm ti omap5 - dra7xx_evm arm armv7 dra7xx ti omap5 - s5p_goni arm armv7 goni samsung s5pc1xx - smdkc100 arm armv7 smdkc100 samsung s5pc1xx - origen arm armv7 origen samsung exynos - s5pc210_universal arm armv7 universal_c210 samsung exynos - snow arm armv7 smdk5250 samsung exynos - smdk5250 arm armv7 smdk5250 samsung exynos - smdkv310 arm armv7 smdkv310 samsung exynos - trats arm armv7 trats samsung exynos - harmony arm armv7:arm720t harmony nvidia tegra20 - seaboard arm armv7:arm720t seaboard nvidia tegra20 - ventana arm armv7:arm720t ventana nvidia tegra20 - whistler arm armv7:arm720t whistler nvidia tegra20 - cardhu arm armv7:arm720t cardhu nvidia tegra30 - beaver arm armv7:arm720t beaver nvidia tegra30 - dalmore arm armv7:arm720t dalmore nvidia tegra114 - colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20 - u8500_href arm armv7 u8500 st-ericsson u8500 - snowball arm armv7 snowball st-ericsson u8500 - kzm9g arm armv7 kzm9g kmc rmobile - armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile - socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga - actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 - actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB - actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 - actux1_8_32 arm ixp actux1 - - actux1:FLASH1X8,RAM_32MB - actux2 arm ixp - actux3 arm ixp - actux4 arm ixp - dvlhost arm ixp - pdnb3 arm ixp pdnb3 prodrive - scpu arm ixp pdnb3 prodrive - pdnb3:SCPU - balloon3 arm pxa - h2200 arm pxa - lp8x4x arm pxa lp8x4x icpdas - lubbock arm pxa - palmld arm pxa - palmtc arm pxa - palmtreo680 arm pxa - polaris arm pxa trizepsiv - - trizepsiv:POLARIS - pxa255_idp arm pxa - trizepsiv arm pxa - vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M - vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M - vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M - xaeniax arm pxa - zipitz2 arm pxa - colibri_pxa270 arm pxa - toradex - jornada arm sa1100 - plutux arm armv7:arm720t plutux avionic-design tegra20 - medcom-wide arm armv7:arm720t medcom-wide avionic-design tegra20 - tec arm armv7:arm720t tec avionic-design tegra20 - paz00 arm armv7:arm720t paz00 compal tegra20 - trimslice arm armv7:arm720t trimslice compulab tegra20 - atngw100 avr32 at32ap - atmel at32ap700x - atngw100mkii avr32 at32ap - atmel at32ap700x - atstk1002 avr32 at32ap atstk1000 atmel at32ap700x - atstk1003 avr32 at32ap atstk1000 atmel at32ap700x - atstk1004 avr32 at32ap atstk1000 atmel at32ap700x - atstk1006 avr32 at32ap atstk1000 atmel at32ap700x - favr-32-ezkit avr32 at32ap - earthlcd at32ap700x - grasshopper avr32 at32ap - in-circuit at32ap700x - mimc200 avr32 at32ap - mimc at32ap700x - hammerhead avr32 at32ap - miromico at32ap700x - bct-brettl2 blackfin blackfin - bf506f-ezkit blackfin blackfin - bf518f-ezbrd blackfin blackfin - bf525-ucr2 blackfin blackfin - bf526-ezbrd blackfin blackfin - bf527-ad7160-eval blackfin blackfin - bf527-ezkit blackfin blackfin - bf527-ezkit-v2 blackfin blackfin bf527-ezkit - - bf527-ezkit:BF527_EZKIT_REV_2_1 - bf527-sdp blackfin blackfin - bf533-ezkit blackfin blackfin - bf533-stamp blackfin blackfin - bf537-minotaur blackfin blackfin - bf537-pnav blackfin blackfin - bf537-srv1 blackfin blackfin - bf537-stamp blackfin blackfin - bf538f-ezkit blackfin blackfin - bf548-ezkit blackfin blackfin - bf561-acvilon blackfin blackfin - bf561-ezkit blackfin blackfin - bf609-ezkit blackfin blackfin - blackstamp blackfin blackfin - blackvme blackfin blackfin - br4 blackfin blackfin - cm-bf527 blackfin blackfin - cm-bf533 blackfin blackfin - cm-bf537e blackfin blackfin - cm-bf537u blackfin blackfin - cm-bf548 blackfin blackfin - cm-bf561 blackfin blackfin - dnp5370 blackfin blackfin - ibf-dsp561 blackfin blackfin - ip04 blackfin blackfin - pr1 blackfin blackfin - tcm-bf518 blackfin blackfin - tcm-bf537 blackfin blackfin - M52277EVB m68k mcf5227x m52277evb freescale - M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 - M52277EVB_stmicro m68k mcf5227x m52277evb freescale - M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 - M5235EVB m68k mcf523x m5235evb freescale - M5235EVB:SYS_TEXT_BASE=0xFFE00000 - M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 - cobra5272 m68k mcf52x2 cobra5272 - - idmr m68k mcf52x2 - eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 - eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 - TASREG m68k mcf52x2 tasreg esd - M5208EVBE m68k mcf52x2 m5208evbe freescale - M5249EVB m68k mcf52x2 m5249evb freescale - M5253DEMO m68k mcf52x2 m5253demo freescale - M5253EVBE m68k mcf52x2 m5253evbe freescale - M5271EVB m68k mcf52x2 m5271evb freescale - M5272C3 m68k mcf52x2 m5272c3 freescale - M5275EVB m68k mcf52x2 m5275evb freescale - M5282EVB m68k mcf52x2 m5282evb freescale - astro_mcf5373l m68k mcf532x mcf5373l astro - M53017EVB m68k mcf532x m53017evb freescale - M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0 - M5329BFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=16 - M5373EVB m68k mcf532x m5373evb freescale - M5373EVB:NANDFLASH_SIZE=16 - M54418TWR m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - M54418TWR_nand_mii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - M54418TWR_nand_rmii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - M54418TWR_nand_rmii_lowfreq m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - M54418TWR_serial_mii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - M54418TWR_serial_rmii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - M54451EVB m68k mcf5445x m54451evb freescale - M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 - M54451EVB_stmicro m68k mcf5445x m54451evb freescale - M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 - M54455EVB m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 - M54455EVB_a66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 - M54455EVB_i66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 - M54455EVB_intel m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 - M54455EVB_stm33 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 - M5475AFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 - M5475BFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 - M5475CFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL - M5475DFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL - M5475EFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL - M5475FFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 - M5475GFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 - M5485AFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 - M5485BFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 - M5485CFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL - M5485DFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL - M5485EFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL - M5485FFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 - M5485GFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 - M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO - microblaze-generic microblaze microblaze microblaze-generic xilinx - qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN - qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN - qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN - qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN - vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM - vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC - vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND - vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE - vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE - vct_platinum_onenand mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND - vct_platinum_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - vct_platinum_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_SMALL_IMAGE - vct_premium mips mips32 vct micronas - vct:VCT_PREMIUM - vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND - vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE - vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE - dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000 - dbau1100 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1100 - dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500 - dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550 - dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN - pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000 - incaip mips mips32 incaip - incaip - incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 - incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 - incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 - adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101 - adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101 - adp-ag102 nds32 n1213 adp-ag102 AndesTech ag102 - nios2-generic nios2 nios2 nios2-generic altera - PCI5441 nios2 nios2 pci5441 psyent - PK1C20 nios2 nios2 pk1c20 psyent - openrisc-generic openrisc or1200 openrisc-generic openrisc - - EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260 - EVB64260_750CX powerpc 74xx_7xx evb64260 - - EVB64260 - P3G4 powerpc 74xx_7xx evb64260 - ppmc7xx powerpc 74xx_7xx - ZUMA powerpc 74xx_7xx evb64260 - ELPPC powerpc 74xx_7xx elppc eltec - CPCI750 powerpc 74xx_7xx cpci750 esd - mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale - DB64360 powerpc 74xx_7xx db64360 Marvell - DB64460 powerpc 74xx_7xx db64460 Marvell - p3m7448 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M7448 - p3m750 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M750 - pdm360ng powerpc mpc512x - aria powerpc mpc512x - davedenx - mecp5123 powerpc mpc512x - esd - mpc5121ads powerpc mpc512x mpc5121ads freescale - mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2 - ac14xx powerpc mpc512x ac14xx ifm - cmi_mpc5xx powerpc mpc5xx cmi - PATI powerpc mpc5xx pati mpl - a3m071 powerpc mpc5xxx a3m071 - a4m072 powerpc mpc5xxx a4m072 - a4m2k powerpc mpc5xxx a3m071 - - a3m071:A4M2K - BC3450 powerpc mpc5xxx bc3450 - canmb powerpc mpc5xxx - cm5200 powerpc mpc5xxx - galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200 - galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT - icecube_5200 powerpc mpc5xxx icecube - - IceCube - icecube_5200_DDR powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR - icecube_5200_DDR_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - icecube_5200_DDR_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - icecube_5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000 - icecube_5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000 - inka4x0 powerpc mpc5xxx - ipek01 powerpc mpc5xxx - jupiter powerpc mpc5xxx - Lite5200 powerpc mpc5xxx icecube - - IceCube - lite5200b powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B - lite5200b_LOWBOOT powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 - lite5200b_PM powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM - Lite5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000 - Lite5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000 - mcc200 powerpc mpc5xxx mcc200 - - mcc200 - mcc200_COM12 powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12 - mcc200_COM12_highboot powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 - mcc200_COM12_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - mcc200_COM12_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,MCC200_SDRAM - mcc200_highboot powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000 - mcc200_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - mcc200_SDRAM powerpc mpc5xxx mcc200 - - mcc200:MCC200_SDRAM - motionpro powerpc mpc5xxx - munices powerpc mpc5xxx - PM520 powerpc mpc5xxx pm520 - PM520_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR - PM520_ROMBOOT powerpc mpc5xxx pm520 - - PM520:BOOT_ROM - PM520_ROMBOOT_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR,BOOT_ROM - prs200 powerpc mpc5xxx mcc200 - - mcc200:PRS200,MCC200_SDRAM - prs200_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200 - prs200_highboot powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - prs200_highboot_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 - Total5200 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1 - Total5200_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 - Total5200_Rev2 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2 - Total5200_Rev2_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 - v38b powerpc mpc5xxx - EVAL5200 powerpc mpc5xxx top5200 emk - TOP5200:EVAL5200 - MINI5200 powerpc mpc5xxx top5200 emk - TOP5200:MINI5200 - TOP5200 powerpc mpc5xxx top5200 emk - TOP5200:TOP5200 - cpci5200 powerpc mpc5xxx - esd - mecp5200 powerpc mpc5xxx - esd - pf5200 powerpc mpc5xxx - esd - O2D powerpc mpc5xxx o2dnt2 ifm - o2d - O2D300 powerpc mpc5xxx o2dnt2 ifm - o2d300 - O2DNT2 powerpc mpc5xxx o2dnt2 ifm - o2dnt2 - O2DNT2_RAMBOOT powerpc mpc5xxx o2dnt2 ifm - o2dnt2:SYS_TEXT_BASE=0x00100000 - O2I powerpc mpc5xxx o2dnt2 ifm - o2i - O2MNT powerpc mpc5xxx o2dnt2 ifm - o2mnt - O2MNT_O2M110 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M110" - O2MNT_O2M112 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M112" - O2MNT_O2M113 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M113" - O3DNT powerpc mpc5xxx o2dnt2 ifm - o3dnt - digsy_mtc powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000 - digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:DIGSY_REV5 - digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 - hmi1001 powerpc mpc5xxx - manroland - mucmc52 powerpc mpc5xxx - manroland - uc101 powerpc mpc5xxx - manroland - MVBC_P powerpc mpc5xxx mvbc_p matrix_vision - MVBC_P:MVBC_P - MVSMR powerpc mpc5xxx mvsmr matrix_vision - pcm030 powerpc mpc5xxx pcm030 phytec - pcm030 - pcm030_LOWBOOT powerpc mpc5xxx pcm030 phytec - pcm030:SYS_TEXT_BASE=0xFF000000 - aev powerpc mpc5xxx tqm5200 tqc - cam5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B - cam5200_niosflash powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH - charon powerpc mpc5xxx tqm5200 tqc - charon - fo300 powerpc mpc5xxx tqm5200 tqc - TQM5200:FO300 - MiniFAP powerpc mpc5xxx tqm5200 tqc - TQM5200:MINIFAP - TB5200 powerpc mpc5xxx tqm5200 tqc - TB5200_B powerpc mpc5xxx tqm5200 tqc - TB5200:TQM5200_B - TQM5200 powerpc mpc5xxx tqm5200 tqc - TQM5200: - TQM5200_B powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B - TQM5200_B_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 - TQM5200S powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S - TQM5200S_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 - TQM5200_STK100 powerpc mpc5xxx tqm5200 tqc - TQM5200:STK52XX_REV100 - A3000 powerpc mpc824x a3000 - CPC45 powerpc mpc824x cpc45 - - CPC45 - CPC45_ROMBOOT powerpc mpc824x cpc45 - - CPC45:BOOT_ROM - CU824 powerpc mpc824x cu824 - eXalion powerpc mpc824x eXalion - HIDDEN_DRAGON powerpc mpc824x hidden_dragon - linkstation_HGLAN powerpc mpc824x linkstation - - linkstation:HGLAN=1 - MOUSSE powerpc mpc824x mousse - MUSENKI powerpc mpc824x musenki - MVBLUE powerpc mpc824x mvblue - PN62 powerpc mpc824x pn62 - Sandpoint8240 powerpc mpc824x sandpoint - Sandpoint8245 powerpc mpc824x sandpoint - utx8245 powerpc mpc824x - debris powerpc mpc824x - etin - kvme080 powerpc mpc824x - etin - atc powerpc mpc8260 - cogent_mpc8260 powerpc mpc8260 cogent - CPU86 powerpc mpc8260 cpu86 - - CPU86 - CPU86_ROMBOOT powerpc mpc8260 cpu86 - - CPU86:BOOT_ROM - CPU87 powerpc mpc8260 cpu87 - - CPU87 - CPU87_ROMBOOT powerpc mpc8260 cpu87 - - CPU87:BOOT_ROM - ep8248 powerpc mpc8260 ep8248 - ep8248E powerpc mpc8260 ep8248 - - ep8248 - ep8260 powerpc mpc8260 - ep82xxm powerpc mpc8260 - gw8260 powerpc mpc8260 - hymod powerpc mpc8260 - IDS8247 powerpc mpc8260 ids8247 - IPHASE4539 powerpc mpc8260 iphase4539 - ISPAN powerpc mpc8260 ispan - ISPAN_REVB powerpc mpc8260 ispan - - ISPAN:SYS_REV_B - muas3001 powerpc mpc8260 muas3001 - muas3001_dev powerpc mpc8260 muas3001 - - muas3001:MUAS_DEV_BOARD - PM825 powerpc mpc8260 pm826 - - PM826:PCI,SYS_TEXT_BASE=0xFF000000 - PM825_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 - PM825_ROMBOOT powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - PM825_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 - PM826 powerpc mpc8260 pm826 - - PM826:SYS_TEXT_BASE=0xFF000000 - PM826_BIGFLASH powerpc mpc8260 pm826 - - PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 - PM826_ROMBOOT powerpc mpc8260 pm826 - - PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - PM826_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 - PM828 powerpc mpc8260 pm828 - - PM828 - PM828_PCI powerpc mpc8260 pm828 - - PM828:PCI - PM828_ROMBOOT powerpc mpc8260 pm828 - - PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - PM828_ROMBOOT_PCI powerpc mpc8260 pm828 - - PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - ppmc8260 powerpc mpc8260 - Rattler powerpc mpc8260 rattler - - Rattler - Rattler8248 powerpc mpc8260 rattler - - Rattler:MPC8248 - RPXsuper powerpc mpc8260 rpxsuper - rsdproto powerpc mpc8260 - sacsng powerpc mpc8260 - ZPC1900 powerpc mpc8260 zpc1900 - MPC8260ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS - MPC8260ADS_33MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 - MPC8260ADS_33MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 - MPC8260ADS_40MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 - MPC8260ADS_40MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 - MPC8260ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 - MPC8266ADS powerpc mpc8260 mpc8266ads freescale - MPC8272ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS - MPC8272ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 - PQ2FADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS - PQ2FADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 - PQ2FADS-VR powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 - PQ2FADS-VR_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 - PQ2FADS-ZU powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS - PQ2FADS-ZU_66MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 - PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 - PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 - VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz - mgcoge powerpc mpc8260 km82xx keymile - km82xx:MGCOGE - mgcoge3ne powerpc mpc8260 km82xx keymile - km82xx:MGCOGE3NE - TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz - TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz - TQM8260_AB powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x - TQM8260_AC powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x - TQM8260_AD powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x - TQM8260_AE powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,266MHz - TQM8260_AF powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x - TQM8260_AG powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz - TQM8260_AH powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x - TQM8260_AI powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x - TQM8265_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8265,300MHz,BUSMODE_60x - TQM8272 powerpc mpc8260 tqm8272 tqc - mpc8308_p1m powerpc mpc83xx - sbc8349 powerpc mpc83xx sbc8349 - - sbc8349 - sbc8349_PCI_33 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_33M - sbc8349_PCI_66 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_66M - ve8313 powerpc mpc83xx ve8313 - caddy2 powerpc mpc83xx vme8349 esd - vme8349:CADDY2 - vme8349 powerpc mpc83xx vme8349 esd - vme8349 - MPC8308RDB powerpc mpc83xx mpc8308rdb freescale - MPC8313ERDB_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ - MPC8313ERDB_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ - MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND - MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND - MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB - MPC8315ERDB_NAND powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB:NAND_U_BOOT - MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale - MPC832XEMDS powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS: - MPC832XEMDS_ATM powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 - MPC832XEMDS_HOST_33 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 - MPC832XEMDS_HOST_66 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 - MPC832XEMDS_SLAVE powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCISLAVE - MPC8349EMDS powerpc mpc83xx mpc8349emds freescale - MPC8349ITX powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX - MPC8349ITXGP powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 - MPC8349ITX_LOWBOOT powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 - MPC8360EMDS_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ - MPC8360EMDS_33_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 - MPC8360EMDS_33_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 - MPC8360EMDS_33_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 - MPC8360EMDS_33_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE - MPC8360EMDS_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ - MPC8360EMDS_66_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 - MPC8360EMDS_66_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 - MPC8360EMDS_66_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 - MPC8360EMDS_66_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE - MPC8360ERDK powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK - MPC8360ERDK_33 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK:CLKIN_33MHZ - MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK - MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS - MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI - MPC837XERDB powerpc mpc83xx mpc837xerdb freescale - kmcoge5ne powerpc mpc83xx km83xx keymile - km8360:KMCOGE5NE - kmeter1 powerpc mpc83xx km83xx keymile - km8360:KMETER1 - MERGERBOX powerpc mpc83xx mergerbox matrix_vision - MVBLM7 powerpc mpc83xx mvblm7 matrix_vision - SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP - SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP - TQM834x powerpc mpc83xx tqm834x tqc - suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3 - kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1 - tuge1 powerpc mpc83xx km83xx keymile - tuxx1:TUGE1 - tuxx1 powerpc mpc83xx km83xx keymile - tuxx1:TUXX1 - kmopti2 powerpc mpc83xx km83xx keymile - tuxx1:KMOPTI2 - kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KMSUPX5 - sbc8548 powerpc mpc85xx sbc8548 - - sbc8548 - sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33 - sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE - sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66 - sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE - socrates powerpc mpc85xx socrates - HWW1U1A powerpc mpc85xx hww1u1a exmeritus - MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS - MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT - MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND - MPC8536DS_SDCARD powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SDCARD - MPC8536DS_SPIFLASH powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SPIFLASH - MPC8540ADS powerpc mpc85xx mpc8540ads freescale - MPC8541CDS powerpc mpc85xx mpc8541cds freescale - MPC8541CDS - MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY - MPC8544DS powerpc mpc85xx mpc8544ds freescale - MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS - MPC8548CDS_36BIT powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:36BIT - MPC8548CDS_legacy powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:LEGACY - MPC8555CDS powerpc mpc85xx mpc8555cds freescale - MPC8555CDS - MPC8555CDS_legacy powerpc mpc85xx mpc8555cds freescale - MPC8555CDS:LEGACY - MPC8560ADS powerpc mpc85xx mpc8560ads freescale - MPC8568MDS powerpc mpc85xx mpc8568mds freescale - MPC8569MDS powerpc mpc85xx mpc8569mds freescale - MPC8569MDS - MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:ATM - MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND - MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS - MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT - MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND - P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND - P1010RDB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT - P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT - P1010RDB_36BIT_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SECURE_BOOT - P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD - P1010RDB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH - P1010RDB_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT - P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND - P1010RDB_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT - P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB - P1010RDB_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SECURE_BOOT - P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD - P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH - P1010RDB_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT - P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB - P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT - P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD - P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SPIFLASH - P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND - P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD - P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH - P1020MBG-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG - P1020MBG-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,36BIT - P1020MBG-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT - P1020MBG-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD - P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB - P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT - P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD - P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH - P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND - P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB - P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT - P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,NAND - P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SDCARD - P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SPIFLASH - P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,NAND - P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SDCARD - P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SPIFLASH - P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD - P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH - P1020UTM-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM - P1020UTM-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT - P1020UTM-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD - P1020UTM-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,SDCARD - P1021RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB - P1021RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT - P1021RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,NAND - P1021RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD - P1021RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH - P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,NAND - P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD - P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH - P1022DS powerpc mpc85xx p1022ds freescale - P1022DS_NAND powerpc mpc85xx p1022ds freescale - P1022DS:NAND - P1022DS_36BIT_NAND powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,NAND - P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH - P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH - P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD - P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD - P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT - P1023RDB powerpc mpc85xx p1023rdb freescale - P1023RDB - P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS - P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND - P1024RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB - P1024RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,36BIT - P1024RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,NAND - P1024RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SDCARD - P1024RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SPIFLASH - P1025RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB - P1025RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,36BIT - P1025RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,NAND - P1025RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SDCARD - P1025RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SPIFLASH - P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB - P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT - P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD - P2010RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SPIFLASH - P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND - P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD - P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH - P2020COME_SDCARD powerpc mpc85xx p2020come freescale - P2020COME:SDCARD - P2020COME_SPIFLASH powerpc mpc85xx p2020come freescale - P2020COME:SPIFLASH - P2020DS powerpc mpc85xx p2020ds freescale - P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT - P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 - P2020DS_SDCARD powerpc mpc85xx p2020ds freescale - P2020DS:SDCARD - P2020DS_SPIFLASH powerpc mpc85xx p2020ds freescale - P2020DS:SPIFLASH - P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB - P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT - P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD - P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SPIFLASH - P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND - P2020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB - P2020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT - P2020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,NAND - P2020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD - P2020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH - P2020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,NAND - P2020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SDCARD - P2020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SPIFLASH - P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD - P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH - P2041RDB powerpc mpc85xx p2041rdb freescale - P2041RDB_NAND powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT - P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - P2041RDB_SRIO_PCIE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - P3041DS powerpc mpc85xx corenet_ds freescale - P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT - P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - P3041DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - P4080DS powerpc mpc85xx corenet_ds freescale - P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT - P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - P4080DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - P5020DS powerpc mpc85xx corenet_ds freescale - P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT - P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - P5040DS powerpc mpc85xx corenet_ds freescale - P5040DS_NAND powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - P5040DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - P5040DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH - BSC9131RDB_SPIFLASH_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 - BSC9131RDB_NAND powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND - BSC9131RDB_NAND_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 - BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 - BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 - BSC9132QDS_NAND_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 - BSC9132QDS_NAND_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 - BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 - BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 - BSC9132QDS_SPIFLASH_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 - BSC9132QDS_SPIFLASH_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 - controlcenterd_36BIT_SDCARD powerpc mpc85xx p1022 gdsys - controlcenterd:36BIT,SDCARD - controlcenterd_36BIT_SDCARD_DEVELOP powerpc mpc85xx p1022 gdsys - controlcenterd:36BIT,SDCARD,DEVELOP - controlcenterd_TRAILBLAZER powerpc mpc85xx p1022 gdsys - controlcenterd:TRAILBLAZER,SPIFLASH - controlcenterd_TRAILBLAZER_DEVELOP powerpc mpc85xx p1022 gdsys - controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP - stxgp3 powerpc mpc85xx stxgp3 stx - stxssa powerpc mpc85xx stxssa stx - stxssa - stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M - T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240 - T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - T4160QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160 - T4160QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - T4160QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860 - B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - B4860QDS_SRIO_PCIE_BOOT powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - B4420QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420 - B4420QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - B4420QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - xpedite520x powerpc mpc85xx - xes - xpedite537x powerpc mpc85xx - xes - xpedite550x powerpc mpc85xx - xes - sbc8641d powerpc mpc86xx - MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale - MPC8641HPCN powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN - MPC8641HPCN_36BIT powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN:PHYS_64BIT - xpedite517x powerpc mpc86xx - xes - Adder powerpc mpc8xx adder - Adder87x powerpc mpc8xx adder - - Adder - AdderII powerpc mpc8xx adder - - Adder:MPC852T - AdderUSB powerpc mpc8xx adder - - Adder - ADS860 powerpc mpc8xx fads - cogent_mpc8xx powerpc mpc8xx cogent - ESTEEM192E powerpc mpc8xx esteem192e - FADS823 powerpc mpc8xx fads - FADS850SAR powerpc mpc8xx fads - FADS860T powerpc mpc8xx fads - FLAGADM powerpc mpc8xx flagadm - GEN860T powerpc mpc8xx gen860t - GEN860T_SC powerpc mpc8xx gen860t - - GEN860T:SC - GENIETV powerpc mpc8xx genietv - hermes powerpc mpc8xx - ICU862 powerpc mpc8xx icu862 - ICU862_100MHz powerpc mpc8xx icu862 - - ICU862:100MHz - IP860 powerpc mpc8xx ip860 - IVML24 powerpc mpc8xx ivm - - IVML24:IVML24_16M - IVML24_128 powerpc mpc8xx ivm - - IVML24:IVML24_32M - IVML24_256 powerpc mpc8xx ivm - - IVML24:IVML24_64M - IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M - IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M - IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M - lwmon powerpc mpc8xx - MBX powerpc mpc8xx mbx8xx - MBX860T powerpc mpc8xx mbx8xx - MPC86xADS powerpc mpc8xx fads - MPC885ADS powerpc mpc8xx fads - NETPHONE powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=1 - NETPHONE_V2 powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=2 - NETTA powerpc mpc8xx netta - - NETTA - NETTA2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=1 - NETTA2_V2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=2 - NETTA_6412 powerpc mpc8xx netta - - NETTA:NETTA_6412=1 - NETTA_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 - NETTA_ISDN powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1 - NETTA_ISDN_6412 powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1 - NETTA_ISDN_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 - NETTA_ISDN_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 - NETTA_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_SWAPHOOK=1 - NETVIA powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=1 - NETVIA_V2 powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=2 - NX823 powerpc mpc8xx nx823 - quantum powerpc mpc8xx - R360MPI powerpc mpc8xx r360mpi - RBC823 powerpc mpc8xx rbc823 - RPXClassic powerpc mpc8xx - RPXlite powerpc mpc8xx - RPXlite_DW powerpc mpc8xx RPXlite_dw - - RPXlite_DW - RPXlite_DW_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz - RPXlite_DW_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 - RPXlite_DW_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20 - RPXlite_DW_NVRAM powerpc mpc8xx RPXlite_dw - - RPXlite_DW:ENV_IS_IN_NVRAM - RPXlite_DW_NVRAM_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM - RPXlite_DW_NVRAM_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - RPXlite_DW_NVRAM_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - RRvision powerpc mpc8xx - RRvision_LCD powerpc mpc8xx RRvision - - RRvision:LCD,SHARP_LQ104V7DS01 - spc1920 powerpc mpc8xx - SPD823TS powerpc mpc8xx spd8xx - svm_sc8xx powerpc mpc8xx - SXNI855T powerpc mpc8xx sixnet - v37 powerpc mpc8xx - MHPC powerpc mpc8xx mhpc eltec - TOP860 powerpc mpc8xx top860 emk - KUP4K powerpc mpc8xx kup4k kup - KUP4X powerpc mpc8xx kup4x kup - ELPT860 powerpc mpc8xx elpt860 LEOX - uc100 powerpc mpc8xx - manroland - QS823 powerpc mpc8xx qs850 snmc - QS850 powerpc mpc8xx qs850 snmc - QS860T powerpc mpc8xx qs860t snmc - stxxtc powerpc mpc8xx stxxtc stx - FPS850L powerpc mpc8xx tqm8xx tqc - FPS860L powerpc mpc8xx tqm8xx tqc - NSCU powerpc mpc8xx tqm8xx tqc - SM850 powerpc mpc8xx tqm8xx tqc - TK885D powerpc mpc8xx tqm8xx tqc - TQM823L powerpc mpc8xx tqm8xx tqc - TQM823L_LCD powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,NEC_NL6448BC20 - TQM823M powerpc mpc8xx tqm8xx tqc - TQM850L powerpc mpc8xx tqm8xx tqc - TQM850M powerpc mpc8xx tqm8xx tqc - TQM855L powerpc mpc8xx tqm8xx tqc - TQM855M powerpc mpc8xx tqm8xx tqc - TQM860L powerpc mpc8xx tqm8xx tqc - TQM860M powerpc mpc8xx tqm8xx tqc - TQM862L powerpc mpc8xx tqm8xx tqc - TQM862M powerpc mpc8xx tqm8xx tqc - TQM866M powerpc mpc8xx tqm8xx tqc - TQM885D powerpc mpc8xx tqm8xx tqc - TTTech powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ104V7DS01 - virtlab2 powerpc mpc8xx tqm8xx tqc - wtk powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ065T9DR51U - csb272 powerpc ppc4xx - csb472 powerpc ppc4xx - G2000 powerpc ppc4xx g2000 - JSE powerpc ppc4xx jse - korat powerpc ppc4xx - korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT - lwmon5 powerpc ppc4xx - lcd4_lwmon5 powerpc ppc4xx lwmon5 - - lwmon5:LCD4_LWMON5 - pcs440ep powerpc ppc4xx - quad100hd powerpc ppc4xx - sbc405 powerpc ppc4xx - sc3 powerpc ppc4xx - t3corp powerpc ppc4xx - W7OLMC powerpc ppc4xx w7o - W7OLMG powerpc ppc4xx w7o - zeus powerpc ppc4xx - acadia powerpc ppc4xx - amcc - acadia_nand powerpc ppc4xx acadia amcc - acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - arches powerpc ppc4xx canyonlands amcc - canyonlands:ARCHES - bamboo powerpc ppc4xx - amcc - bamboo_nand powerpc ppc4xx bamboo amcc - bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - bluestone powerpc ppc4xx - amcc - bubinga powerpc ppc4xx - amcc - canyonlands powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS - canyonlands_nand powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - ebony powerpc ppc4xx - amcc - glacier powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER - glacier_nand powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - haleakala powerpc ppc4xx kilauea amcc - kilauea:HALEAKALA - haleakala_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - katmai powerpc ppc4xx - amcc - kilauea powerpc ppc4xx kilauea amcc - kilauea:KILAUEA - kilauea_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - luan powerpc ppc4xx - amcc - makalu powerpc ppc4xx - amcc - ocotea powerpc ppc4xx - amcc - rainier powerpc ppc4xx sequoia amcc - sequoia:RAINIER - rainier_nand powerpc ppc4xx sequoia amcc - sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - rainier_ramboot powerpc ppc4xx sequoia amcc - sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds - redwood powerpc ppc4xx - amcc - sequoia powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA - sequoia_nand powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 - sequoia_ramboot powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds - sycamore powerpc ppc4xx walnut amcc - walnut - taihu powerpc ppc4xx - amcc - taishan powerpc ppc4xx - amcc - walnut powerpc ppc4xx walnut amcc - yellowstone powerpc ppc4xx yosemite amcc - yosemite:YELLOWSTONE - yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE - yucca powerpc ppc4xx - amcc - CRAYL1 powerpc ppc4xx L1 cray - CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1 - CATcenter_25 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - CATcenter_33 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - PPChameleonEVB powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB_BA_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 - PPChameleonEVB_BA_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 - PPChameleonEVB_HI_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 - PPChameleonEVB_HI_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 - PPChameleonEVB_ME_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - PPChameleonEVB_ME_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - APC405 powerpc ppc4xx apc405 esd - AR405 powerpc ppc4xx ar405 esd - ASH405 powerpc ppc4xx ash405 esd - CANBT powerpc ppc4xx canbt esd - CMS700 powerpc ppc4xx cms700 esd - CPCI2DP powerpc ppc4xx cpci2dp esd - CPCI405 powerpc ppc4xx cpci405 esd - CPCI4052 powerpc ppc4xx cpci405 esd - CPCI405AB powerpc ppc4xx cpci405 esd - CPCI405DT powerpc ppc4xx cpci405 esd - CPCIISER4 powerpc ppc4xx cpciiser4 esd - DP405 powerpc ppc4xx dp405 esd - DU405 powerpc ppc4xx du405 esd - DU440 powerpc ppc4xx du440 esd - HH405 powerpc ppc4xx hh405 esd - HUB405 powerpc ppc4xx hub405 esd - OCRTC powerpc ppc4xx ocrtc esd - PCI405 powerpc ppc4xx pci405 esd - PLU405 powerpc ppc4xx plu405 esd - PMC405 powerpc ppc4xx pmc405 esd - PMC405DE powerpc ppc4xx pmc405de esd - PMC440 powerpc ppc4xx pmc440 esd - VOH405 powerpc ppc4xx voh405 esd - VOM405 powerpc ppc4xx vom405 esd - WUH405 powerpc ppc4xx wuh405 esd - devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER - dlvision powerpc ppc4xx - gdsys - dlvision-10g powerpc ppc4xx 405ep gdsys - gdppc440etx powerpc ppc4xx - gdsys - intip powerpc ppc4xx intip gdsys - intip:INTIB - io powerpc ppc4xx 405ep gdsys - io64 powerpc ppc4xx 405ex gdsys - iocon powerpc ppc4xx 405ep gdsys - neo powerpc ppc4xx 405ep gdsys - icon powerpc ppc4xx - mosaixtech - MIP405 powerpc ppc4xx mip405 mpl - MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T - PIP405 powerpc ppc4xx pip405 mpl - alpr powerpc ppc4xx - prodrive - p3p440 powerpc ppc4xx - prodrive - KAREF powerpc ppc4xx karef sandburst - METROBOX powerpc ppc4xx metrobox sandburst - xpedite1000 powerpc ppc4xx - xes - xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - - xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - - sandbox sandbox sandbox sandbox sandbox - - rsk7203 sh sh2 rsk7203 renesas - - rsk7264 sh sh2 rsk7264 renesas - - rsk7269 sh sh2 rsk7269 renesas - - mpr2 sh sh3 mpr2 - - - ms7720se sh sh3 ms7720se - - - shmin sh sh3 shmin - - - espt sh sh4 espt - - - ms7722se sh sh4 ms7722se - - - ms7750se sh sh4 ms7750se - - - ap325rxa sh sh4 ap325rxa renesas - - ecovec sh sh4 ecovec renesas - - MigoR sh sh4 MigoR renesas - - r2dplus sh sh4 r2dplus renesas - - r7780mp sh sh4 r7780mp renesas - - sh7752evb sh sh4 sh7752evb renesas - - sh7757lcr sh sh4 sh7757lcr renesas - - sh7763rdp sh sh4 sh7763rdp renesas - - sh7785lcr sh sh4 sh7785lcr renesas - - sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1 - r0p7734 sh sh4 r0p7734 renesas - - ap_sh4a_4a sh sh4 ap_sh4a_4a alphaproject - - grsim_leon2 sparc leon2 - gaisler - gr_cpci_ax2000 sparc leon3 - gaisler - gr_ep2s60 sparc leon3 - gaisler - grsim sparc leon3 - gaisler - gr_xc3s_1500 sparc leon3 - gaisler - coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000 - # Target ARCH CPU Board name Vendor SoC Options - ######################################################################################################################## + Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij + Active arm arm1136 mx31 - - imx31_phycore - - + Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk + Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam + Active arm arm1136 mx31 hale - tt01 - Helmut Raiger + Active arm arm1136 mx31 logicpd - imx31_litekit - - + Active arm arm1136 mx35 - - woodburn - Stefano Babic + Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg - + Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic + Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic + Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren + Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park + Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij + Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij + Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij + Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang + Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek at91rm9200ek Andreas Bießmann + Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann + Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 eb_cpux9k2 Jens Scharsig + Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig + Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard + Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard + Active arm arm920t imx - - mx1ads - - + Active arm arm920t imx - - scb9328 - Torsten Koschorrek + Active arm arm920t ks8695 - - cm4008 - Greg Ungerer + Active arm arm920t ks8695 - - cm41xx - - + Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau + Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller + Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller + Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij + Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij + Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar + Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav + Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop + Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen + Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu + Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu + Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu + Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop + Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen + Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen + Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen + Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen + Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon + Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon + Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig + Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig + Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre + Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre + Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre + Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre + Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre + Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre + Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH + Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer + Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer + Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski + Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski + Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski + Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski + Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard + Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard + Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard + Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard + Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard + Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard + Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard + Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard + Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev + Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev + Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev + Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig + Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig + Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher + Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher + Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson + Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara + Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara + Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara + Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim :Sughosh Ganu + Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim :Sughosh Ganu + Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj + Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj + Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj + Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj + Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj + Active arm arm926ejs davinci davinci dvevm davinci_dvevm - - + Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic + Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - - + Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - - + Active arm arm926ejs davinci davinci sonata davinci_sonata - - + Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher + Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier :Christian Riesch + Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle + Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle + Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy + Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier + Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov + Active arm arm926ejs kirkwood karo tk71 tk71 - - + Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp + Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp + Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp + Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp + Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp + Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp + Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp + Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 - + Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot + Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot + Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 - + Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot + Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 - + Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot + Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - - + Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper + Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore + Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar + Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar + Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar + Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar + Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT - + Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE - + Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov + Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper + Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami + Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy + Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser + Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam + Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby + Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser + Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes :Eric Jarrige + Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk + Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher + Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala + Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut + Active arm arm926ejs mxs denx m28evk m28evk m28evk Marek Vasut + Active arm arm926ejs mxs freescale mx23evk mx23evk mx23evk Otavio Salvador + Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam + Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam + Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam + Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut + Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut + Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut + Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team :Alessandro Rubini + Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team :Alessandro Rubini + Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya + Active arm arm926ejs omap ti omap730p2 omap730p2 omap730p2:CS3_BOOT Dave Peverley + Active arm arm926ejs omap ti omap730p2 omap730p2_cs0boot omap730p2:CS0_BOOT Dave Peverley + Active arm arm926ejs omap ti omap730p2 omap730p2_cs3boot omap730p2:CS3_BOOT Dave Peverley + Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD + Active arm arm926ejs pantheon Marvell - dkb - Lei Wen + Active arm arm926ejs spear spear - x600 x600 Stefan Roese + Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar + Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand - + Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty - + Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand - + Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar + Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand - + Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR - + Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty - + Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand - + Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR - + Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar + Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand - + Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR - + Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty - + Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand - + Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR - + Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar + Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand - + Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty - + Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand - + Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB - + Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB - + Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB - + Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij + Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij + Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - + Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel + Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel + Active arm armv7 am33xx isee igep0033 igep0033 - Enric Balletbo i Serra + Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel + Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier + Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier + Active arm armv7 am33xx siemens rut rut - Roger Meier + Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=1,NAND Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=1,NAND Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=1,NAND Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=1,NAND Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=1,NAND Tom Rini + Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini + Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 - + Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter + Active arm armv7 am33xx ti ti816x ti816x_evm - - + Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen + Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen + Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen + Active arm armv7 exynos samsung arndale arndale - Inderpal Singh + Active arm armv7 exynos samsung origen origen - Chander Kashyap + Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap + Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde + Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap + Active arm armv7 exynos samsung trats trats - Lukasz Majewski + Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek + Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Minkyu Kang + Active arm armv7 highbank - highbank highbank - Rob Herring + Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut + Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - + Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic + Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam + Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu + Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu + Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam + Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - + Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - + Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic + Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam + Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam + Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam + Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson + Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson + Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson + Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson + Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson + Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson + Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson + Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre + Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu + Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam + Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam + Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam + Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam + Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese + Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman + Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas + Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat + Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli + Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg + Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber + Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok + Active arm armv7 omap3 isee igep00x0 igep0020 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra + Active arm armv7 omap3 isee igep00x0 igep0020_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - + Active arm armv7 omap3 isee igep00x0 igep0030 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra + Active arm armv7 omap3 isee igep00x0 igep0030_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - + Active arm armv7 omap3 isee igep00x0 igep0032 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra + Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath + Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada + Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon + Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix + Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones + Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár + Active arm armv7 omap3 technexion twister twister - Stefano Babic + Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic + Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S + Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini + Active arm armv7 omap3 ti evm omap3_evm - Tom Rini + Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - - + Active arm armv7 omap3 ti evm omap3_evm_quick_nand - - + Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon + Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber + Active arm armv7 omap4 ti panda omap4_panda - Sricharan R + Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R + Active arm armv7 omap5 ti dra7xx dra7xx_evm - Lokesh Vutla + Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - + Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu + Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu :Tetsuyuki Kobayashi + Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang + Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang + Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - + Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier + Active arm armv7 u8500 st-ericsson u8500 u8500_href - - + Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang -Active arm armv7 zynq xilinx zynq zynq - Michal Simek -Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_zc770_XM010 zynq_zc770:ZC770_XM010 Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_zc770_XM011 zynq_zc770:ZC770_XM011 Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_zc770_XM012 zynq_zc770:ZC770_XM012 Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_zc770_XM013 zynq_zc770:ZC770_XM013 Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_afx_nor zynq_afx:AFX_NOR Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_afx_qspi zynq_afx:AFX_QSPI Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_afx_nand zynq_afx:AFX_NAND Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_cse_nor zynq_cse:CSE_NOR Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_cse_qspi zynq_cse:CSE_QSPI Michal Simek ++Active arm armv7 zynq xilinx zynq zynq_cse_nand zynq_cse:CSE_NAND Michal Simek + Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren + Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding + Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding + Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding + Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren :Stephen Warren + Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren :Stephen Warren + Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren + Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren + Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren :Stephen Warren + Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren :Stephen Warren + Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach + Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren :Stephen Warren + Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren + Active arm ixp - - - actux2 - Michael Schwingen + Active arm ixp - - - actux3 - Michael Schwingen + Active arm ixp - - - actux4 - Michael Schwingen + Active arm ixp - - - dvlhost - Michael Schwingen + Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen + Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen + Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen + Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen + Active arm ixp - prodrive pdnb3 pdnb3 - Stefan Roese + Active arm ixp - prodrive pdnb3 scpu pdnb3:SCPU Stefan Roese + Active arm pxa - - - balloon3 - Marek Vasut + Active arm pxa - - - h2200 - Lukasz Dalek + Active arm pxa - - - palmld - Marek Vasut + Active arm pxa - - - palmtc - Marek Vasut + Active arm pxa - - - palmtreo680 - Mike Dunn + Active arm pxa - - - pxa255_idp - Cliff Brake + Active arm pxa - - - trizepsiv - Stefano Babic + Active arm pxa - - - xaeniax - - + Active arm pxa - - - zipitz2 - Marek Vasut + Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic + Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut + Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut + Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut + Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich + Active arm pxa - toradex - colibri_pxa270 - Marek Vasut + Active arm sa1100 - - - jornada - Kristoffer Ericson + Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen + Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann + Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen + Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen + Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen + Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen + Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt + Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann + Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson + Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May :Alex Raimondi + Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald + Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang :Chong Huang + Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf527-sdp - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf533-stamp - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf537-minotaur - Martin Strubel + Active blackfin blackfin - - - bf537-pnav - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf537-srv1 - Martin Strubel + Active blackfin blackfin - - - bf537-stamp - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin :Valentin Yakovenkov + Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang :Blackfin Team + Active blackfin blackfin - - - blackstamp - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews + Active blackfin blackfin - - - blackvme - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews + Active blackfin blackfin - - - br4 - Dimitar Penev + Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards + Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards + Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards + Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards + Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards + Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards + Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) + Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule + Active blackfin blackfin - - - ip04 - Brent Kandetzki + Active blackfin blackfin - - - pr1 - Dimitar Penev + Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards + Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards + Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang :Blackfin Team + Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew + Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew + Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew + Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew + Active m68k mcf52x2 - - - idmr - - + Active m68k mcf52x2 - - cobra5272 cobra5272 - - + Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig + Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig + Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs + Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - - + Active m68k mcf52x2 - freescale m5249evb M5249EVB - - + Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew + Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser + Active m68k mcf52x2 - freescale m5271evb M5271EVB - - + Active m68k mcf52x2 - freescale m5272c3 M5272C3 - - + Active m68k mcf52x2 - freescale m5275evb M5275EVB - - + Active m68k mcf52x2 - freescale m5282evb M5282EVB - - + Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner + Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew + Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew + Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew + Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew + Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - + Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - + Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - + Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - + Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - + Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - + Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 - + Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 - + Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew + Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew + Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew + Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew + Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew + Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew + Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew + Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew + Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew + Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew + Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew + Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew + Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew + Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek + Active mips mips32 - - qemu-malta qemu_malta qemu-malta:MIPS32,SYS_BIG_ENDIAN - + Active mips mips32 - - qemu-malta qemu_maltael qemu-malta:MIPS32,SYS_LITTLE_ENDIAN - + Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu + Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - + Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM - + Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND - + Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - + Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE - + Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC - + Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND - + Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE - + Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE - + Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM - + Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND - + Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE - + Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE - + Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange + Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange + Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange + Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange + Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange + Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - + Active mips mips32 incaip - incaip incaip - Wolfgang Denk + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk + Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - + Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - + Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes + Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes + Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes + Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt + Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt + Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt + Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson + Active powerpc 74xx_7xx - - - ppmc7xx - - + Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk + Active powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu + Active powerpc 74xx_7xx - eltec elppc ELPPC - - + Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt + Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang + Active powerpc 74xx_7xx - Marvell db64360 DB64360 - - + Active powerpc 74xx_7xx - Marvell db64460 DB64460 - - + Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese + Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese + Active powerpc mpc512x - - - pdm360ng - Michael Weiss + Active powerpc mpc512x - davedenx - aria - Wolfgang Denk + Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt + Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - - + Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 - + Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin + Active powerpc mpc5xx - - cmi cmi_mpc5xx - - + Active powerpc mpc5xx - mpl pati PATI - - + Active powerpc mpc5xxx - - - canmb - - + Active powerpc mpc5xxx - - - cm5200 - - + Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel + Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger + Active powerpc mpc5xxx - - - jupiter - Heiko Schocher + Active powerpc mpc5xxx - - - motionpro - - + Active powerpc mpc5xxx - - - munices - - + Active powerpc mpc5xxx - - - v38b - - + Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese + Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese + Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov + Active powerpc mpc5xxx - - bc3450 BC3450 - - + Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt + Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt + Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk + Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR - + Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - + Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - + Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 - + Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 - + Active powerpc mpc5xxx - - icecube Lite5200 IceCube - + Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 - + Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 - + Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B - + Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 - + Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM - + Active powerpc mpc5xxx - - mcc200 mcc200 mcc200 - + Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 - + Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 - + Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - + Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM - + Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 - + Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - + Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM - + Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM - + Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 - + Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - + Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 - + Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner + Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner + Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner + Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner + Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 - + Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 - + Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 - + Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 - + Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer + Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer + Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer + Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt + Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt + Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt + Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin + Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin + Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister + Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister + Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister + Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister + Active powerpc mpc5xxx - manroland - hmi1001 - - + Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher + Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher + Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz + Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz + Active powerpc mpc5xxx - phytec pcm030 pcm030 pcm030 Jon Smirl + Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl + Active powerpc mpc5xxx - tqc tqm5200 aev - - + Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B - + Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH - + Active powerpc mpc5xxx - tqc tqm5200 charon charon Heiko Schocher + Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 - + Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP - + Active powerpc mpc5xxx - tqc tqm5200 TB5200 - - + Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B - + Active powerpc mpc5xxx - tqc tqm5200 TQM5200 TQM5200: - + Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B - + Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 - + Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 - + Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S - + Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 - + Active powerpc mpc824x - - - utx8245 - Greg Allen + Active powerpc mpc824x - - a3000 A3000 - - + Active powerpc mpc824x - - cpc45 CPC45 CPC45 Josef Wagner + Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner + Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk + Active powerpc mpc824x - - eXalion eXalion - Torsten Demke + Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso + Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski + Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson + Active powerpc mpc824x - - mvblue MVBLUE - - + Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger + Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk + Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson + Active powerpc mpc824x - etin - debris - Sangmoon Kim + Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim + Active powerpc mpc8260 - - - atc - Wolfgang Denk + Active powerpc mpc8260 - - - ep8260 - Frank Panno + Active powerpc mpc8260 - - - ep82xxm - - + Active powerpc mpc8260 - - - gw8260 - Oliver Brown + Active powerpc mpc8260 - - - hymod - Murray Jensen + Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp + Active powerpc mpc8260 - - - sacsng - Jerry Van Baren + Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen + Active powerpc mpc8260 - - cpu86 CPU86 CPU86 Wolfgang Denk + Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk + Active powerpc mpc8260 - - cpu87 CPU87 CPU87 - + Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - + Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen + Active powerpc mpc8260 - - ep8248 ep8248E ep8248 Yuli Barcohen + Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher + Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger + Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen + Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen + Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher + Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher + Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk + Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk + Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk + Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk + Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk + Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk + Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk + Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk + Active powerpc mpc8260 - - pm828 PM828 PM828 - + Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI - + Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - + Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - + Active powerpc mpc8260 - - rattler Rattler Rattler Yuli Barcohen + Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen + Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen + Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen + Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz - + Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck + Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck + Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk + Active powerpc mpc8260 - tqc tqm8272 TQM8272 - - + Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok + Active powerpc mpc83xx - - sbc8349 sbc8349 sbc8349 Paul Gortmaker + Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker + Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker + Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher + Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt + Active powerpc mpc83xx - esd vme8349 vme8349 vme8349 Reinhard Arlt + Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok + Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ - + Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ - + Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND - + Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND - + Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB MPC8315ERDB Dave Liu + Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu + Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski + Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS MPC832XEMDS: Dave Liu + Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu + Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu + Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu + Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu + Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips + Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX - + Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 - + Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 - + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu + Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu + Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK MPC8360ERDK Anton Vorontsov + Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov + Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_66 MPC8360ERDK Anton Vorontsov + Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS MPC837XEMDS Dave Liu + Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu + Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio + Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck + Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck + Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck + Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher + Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck + Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck + Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck + Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck + Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz + Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz + Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid + Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid + Active powerpc mpc83xx - tqc tqm834x TQM834x - - + Active powerpc mpc85xx - - sbc8548 sbc8548 sbc8548 Paul Gortmaker + Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker + Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker + Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker + Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker + Active powerpc mpc85xx - - socrates socrates - - + Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett + Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - + Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - + Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal + Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal + Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal + Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi + Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu + Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu + Active powerpc mpc85xx - freescale corenet_ds P3041DS - - + Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT - + Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P4080DS - - + Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT - + Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P5020DS - - + Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT - + Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P5040DS - - + Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS - + Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT - + Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND - + Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD - + Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH - + Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala + Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS MPC8541CDS Kumar Gala + Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala + Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - - + Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS MPC8548CDS - + Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT - + Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY - + Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS MPC8555CDS Kumar Gala + Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala + Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala + Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - - + Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS MPC8569MDS - + Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - + Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND - + Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS MPC8572DS - + Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT - + Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NAND P1010RDB:P1010RDB,36BIT,NAND - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NOR P1010RDB:P1010RDB,36BIT - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB,36BIT,SECURE_BOOT - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SDCARD P1010RDB:P1010RDB,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SPIFLASH P1010RDB:P1010RDB,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NAND P1010RDB:P1010RDB,NAND - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NAND_SECBOOT P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NOR P1010RDB:P1010RDB - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NOR_SECBOOT P1010RDB:P1010RDB,SECURE_BOOT - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SDCARD P1010RDB:P1010RDB,SDCARD - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SPIFLASH P1010RDB:P1010RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SPIFLASH_SECBOOT P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT - + Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi + Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi + Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi + Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi + Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi + Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi + Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi + Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi + Active powerpc mpc85xx - freescale p1023rdb P1023RDB P1023RDB - + Active powerpc mpc85xx - freescale p1023rds P1023RDS P1023RDS Roy Zang + Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang + Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB - + Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB - + Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB - + Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal + Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD - + Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH - + Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 - + Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder + Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder + Active powerpc mpc85xx - freescale p2020ds P2020DS - - + Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT - + Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 - + Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD - + Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH - + Active powerpc mpc85xx - freescale p2041rdb P2041RDB - - + Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT - + Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - + Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun + Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - + Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - + Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach + Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach + Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach + Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach + Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek + Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek + Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek + Active powerpc mpc85xx - xes - xpedite520x - - + Active powerpc mpc85xx - xes - xpedite537x - - + Active powerpc mpc85xx - xes - xpedite550x - - + Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker + Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - - + Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN MPC8641HPCN Kumar Gala + Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala + Active powerpc mpc86xx - xes - xpedite517x - - + Active powerpc mpc8xx - - - hermes - Wolfgang Denk + Active powerpc mpc8xx - - - lwmon - Wolfgang Denk + Active powerpc mpc8xx - - - quantum - - + Active powerpc mpc8xx - - - RRvision - Wolfgang Denk + Active powerpc mpc8xx - - - spc1920 - - + Active powerpc mpc8xx - - - svm_sc8xx - John Zhan + Active powerpc mpc8xx - - - v37 - - + Active powerpc mpc8xx - - adder Adder - Yuli Barcohen + Active powerpc mpc8xx - - adder Adder87x Adder Yuli Barcohen + Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen + Active powerpc mpc8xx - - adder AdderUSB Adder Yuli Barcohen + Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen + Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark + Active powerpc mpc8xx - - fads MPC86xADS - - + Active powerpc mpc8xx - - fads MPC885ADS - - + Active powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson + Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater + Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater + Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk + Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk + Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk + Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk + Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk + Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk + Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk + Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk + Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk + Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 - + Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 - + Active powerpc mpc8xx - - netta NETTA NETTA - + Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 - + Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 - + Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 - + Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 - + Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 - + Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 - + Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 - + Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 - + Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 - + Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou + Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou + Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk + Active powerpc mpc8xx - - rbc823 RBC823 - - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW RPXlite_DW - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - + Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - + Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk + Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis + Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk + Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling + Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer + Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck + Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck + Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team + Active powerpc mpc8xx - manroland - uc100 - Stefan Roese + Active powerpc mpc8xx - snmc qs850 QS823 - - + Active powerpc mpc8xx - snmc qs850 QS850 - - + Active powerpc mpc8xx - snmc qs860t QS860T - - + Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek + Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx NSCU - - + Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx TK885D - - + Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx TQM823M - - + Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx TQM850M - - + Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx TQM855M - - + Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx TQM860M - - + Active powerpc mpc8xx - tqc tqm8xx TQM862L - - + Active powerpc mpc8xx - tqc tqm8xx TQM862M - - + Active powerpc mpc8xx - tqc tqm8xx TQM866M - - + Active powerpc mpc8xx - tqc tqm8xx TQM885D - - + Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk + Active powerpc mpc8xx - tqc tqm8xx virtlab2 - - + Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk + Active powerpc ppc4xx - - - csb272 - Tolunay Orkun + Active powerpc ppc4xx - - - csb472 - Tolunay Orkun + Active powerpc ppc4xx - - - korat - Larry Johnson + Active powerpc ppc4xx - - - lwmon5 - Stefan Roese + Active powerpc ppc4xx - - - pcs440ep - Stefan Roese + Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn + Active powerpc ppc4xx - - - sbc405 - - + Active powerpc ppc4xx - - - sc3 - Heiko Schocher + Active powerpc ppc4xx - - - t3corp - Stefan Roese + Active powerpc ppc4xx - - - zeus - Stefan Roese + Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs + Active powerpc ppc4xx - - jse JSE - Stephen Williams + Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson + Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese + Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen + Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen + Active powerpc ppc4xx - amcc - acadia - Stefan Roese + Active powerpc ppc4xx - amcc - bamboo - Stefan Roese + Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri + Active powerpc ppc4xx - amcc - bubinga - - + Active powerpc ppc4xx - amcc - ebony - Stefan Roese + Active powerpc ppc4xx - amcc - katmai - Stefan Roese + Active powerpc ppc4xx - amcc - luan - John Otken + Active powerpc ppc4xx - amcc - makalu - Stefan Roese + Active powerpc ppc4xx - amcc - ocotea - Stefan Roese + Active powerpc ppc4xx - amcc - redwood - Feng Kan + Active powerpc ppc4xx - amcc - taihu - John Otken + Active powerpc ppc4xx - amcc - taishan - Stefan Roese + Active powerpc ppc4xx - amcc - yucca - - + Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese + Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese + Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese + Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese + Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese + Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese + Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese + Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese + Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese + Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese + Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese + Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese + Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese + Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese -Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt -Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt -Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda -Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda + Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff + Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 - + Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - + Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - + Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson + Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson + Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson + Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson + Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson + Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson + Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson + Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs + Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs + Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs + Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs + Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs + Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs + Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs + Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs + Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs + Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs + Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs + Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs + Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs + Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs + Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs + Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs + Active powerpc ppc4xx - esd pci405 PCI405 - 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* - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place, Suite 330, Boston, MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The NAND flash driver defines */ +#define ZYNQ_NAND_CMD_PHASE 1 /* End command valid in command phase */ +#define ZYNQ_NAND_DATA_PHASE 2 /* End command valid in data phase */ +#define ZYNQ_NAND_ECC_SIZE 512 /* Size of data for ECC operation */ + +/* Flash memory controller operating parameters */ +#define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \ + (0x1 << 4) | /* Clear interrupt */ \ + (0x1 << 6)) /* Disable ECC interrupt */ + +/* Assuming 50MHz clock (20ns cycle time) and 3V operation */ +#define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \ + (0x2 << 17) | /* t_ar from nand_cycles */ \ + (0x1 << 14) | /* t_clr from nand_cycles */ \ + (0x3 << 11) | /* t_wp from nand_cycles */ \ + (0x2 << 8) | /* t_rea from nand_cycles */ \ + (0x5 << 4) | /* t_wc from nand_cycles */ \ + (0x5 << 0)) /* t_rc from nand_cycles */ + +#define ZYNQ_NAND_SET_OPMODE 0x0 + +#define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \ + (0x2 << 21)) /* UpdateRegs operation */ + +#define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \ + (0x1 << 4) | /* ECC read at end of page */ \ + (0x0 << 5)) /* No Jumping */ + +#define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \ + (0x00 << 8) | /* Read command */ \ + (0x30 << 16) | /* Read End command */ \ + (0x1 << 24)) /* Read End command calid */ + +#define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \ + (0x05 << 8) | /* Read col change cmd */ \ + (0xE0 << 16) | /* Read col change end cmd */ \ + (0x1 << 24)) /* Read col change + end cmd valid */ +/* AXI Address definitions */ +#define START_CMD_SHIFT 3 +#define END_CMD_SHIFT 11 +#define END_CMD_VALID_SHIFT 20 +#define ADDR_CYCLES_SHIFT 21 +#define CLEAR_CS_SHIFT 21 +#define ECC_LAST_SHIFT 10 +#define COMMAND_PHASE (0 << 19) +#define DATA_PHASE (1 << 19) + +#define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */ +#define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */ + +/* ECC block registers bit position and bit mask */ +#define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ +#define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ + +/* NAND MIO buswidth count*/ +#define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13 +#define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8 + +/* NAND buswidth */ +enum zynq_nand_bus_width { + NAND_BW_UNKNOWN = -1, + NAND_BW_8BIT, + NAND_BW_16BIT, +}; + +/* SMC register set */ +struct zynq_nand_smc_regs { + u32 csr; /* 0x00 */ + u32 reserved0[2]; + u32 cfr; /* 0x0C */ + u32 dcr; /* 0x10 */ + u32 scr; /* 0x14 */ + u32 sor; /* 0x18 */ + u32 reserved1[249]; + u32 esr; /* 0x400 */ + u32 emcr; /* 0x404 */ + u32 emcmd1r; /* 0x408 */ + u32 emcmd2r; /* 0x40C */ + u32 reserved2[2]; + u32 eval0r; /* 0x418 */ +}; + +#define zynq_nand_smc_base ((struct zynq_nand_smc_regs *)ZYNQ_SMC_BASEADDR) + +/* + * struct zynq_nand_command_format - Defines NAND flash command format + * @start_cmd: First cycle command (Start command) + * @end_cmd: Second cycle command (Last command) + * @addr_cycles: Number of address cycles required to send the address + * @end_cmd_valid: The second cycle command is valid for cmd or data phase + */ +struct zynq_nand_command_format { + int start_cmd; + int end_cmd; + u8 addr_cycles; + u8 end_cmd_valid; +}; + +/* + * struct zynq_nand_info - Defines the NAND flash driver instance + * @parts: Pointer to the mtd_partition structure + * @nand_base: Virtual address of the NAND flash device + * @end_cmd_pending: End command is pending + * @end_cmd: End command + */ +struct zynq_nand_info { +#ifdef CONFIG_MTD_PARTITIONS + struct mtd_partition *parts; +#endif + void __iomem *nand_base; + unsigned long end_cmd_pending; + unsigned long end_cmd; +}; + +#define ONDIE_ECC_FEATURE_ADDR 0x90 + +/* The NAND flash operations command format */ +static const struct zynq_nand_command_format zynq_nand_commands[] = { + {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_READID, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_STATUS, NAND_CMD_NONE, 0, NAND_CMD_NONE}, + {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE}, + {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, NAND_CMD_NONE}, + {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_RESET, NAND_CMD_NONE, 0, NAND_CMD_NONE}, + {NAND_CMD_PARAM, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0}, + /* Add all the flash commands supported by the flash device and Linux + * The cache program command is not supported by driver because driver + * cant differentiate between page program and cached page program from + * start command, these commands can be differentiated through end + * command, which doesn't fit in to the driver design. The cache program + * command is not supported by NAND subsystem also, look at 1612 line + * number (in nand_write_page function) of nand_base.c file. + * {NAND_CMD_SEQIN, NAND_CMD_CACHEDPROG, 5, ZYNQ_NAND_YES} + */ +}; + +/* Define default oob placement schemes for large and small page devices */ +static struct nand_ecclayout nand_oob_16 = { + .eccbytes = 3, + .eccpos = {13, 14, 15}, + .oobfree = { + { .offset = 0, .length = 12 } + } +}; + +static struct nand_ecclayout nand_oob_64 = { + .eccbytes = 12, + .eccpos = { + 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63}, + .oobfree = { + { .offset = 2, .length = 50 } + } +}; + +static struct nand_ecclayout ondie_nand_oob_64 = { + .eccbytes = 32, + + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 24, 25, 26, 27, 28, 29, 30, 31, + 40, 41, 42, 43, 44, 45, 46, 47, + 56, 57, 58, 59, 60, 61, 62, 63 + }, + + .oobfree = { + { .offset = 4, .length = 4 }, + { .offset = 20, .length = 4 }, + { .offset = 36, .length = 4 }, + { .offset = 52, .length = 4 } + } +}; + +/* Generic flash bbt decriptors */ +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 4, + .len = 4, + .veroffs = 20, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 4, + .len = 4, + .veroffs = 20, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/* + * zynq_nand_waitfor_ecc_completion - Wait for ECC completion + * + * returns: status for command completion, -1 for Timeout + */ +static int zynq_nand_waitfor_ecc_completion(void) +{ + unsigned long timeout; + u32 status; + + /* Wait max 10ms */ + timeout = 10; + status = readl(&zynq_nand_smc_base->esr); + while (status & ZYNQ_NAND_ECC_BUSY) { + status = readl(&zynq_nand_smc_base->esr); + if (timeout == 0) + return -1; + timeout--; + udelay(1); + } + + return status; +} + +/* + * zynq_nand_init_nand_flash - Initialize NAND controller + * @option: Device property flags + * + * This function initializes the NAND flash interface on the NAND controller. + * + * returns: 0 on success or error value on failure + */ +static int zynq_nand_init_nand_flash(int option) +{ + u32 status; + + /* disable interrupts */ + writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr); + /* Initialize the NAND interface by setting cycles and operation mode */ + writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr); + if (option & NAND_BUSWIDTH_16) + writel((ZYNQ_NAND_SET_OPMODE | 0x1), &zynq_nand_smc_base->sor); + else + writel(ZYNQ_NAND_SET_OPMODE, &zynq_nand_smc_base->sor); + + writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr); + + /* Wait till the ECC operation is complete */ + status = zynq_nand_waitfor_ecc_completion(); + if (status < 0) { + printf("%s: Timeout\n", __func__); + return status; + } + + /* Set the command1 and command2 register */ + writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r); + writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r); + + return 0; +} + +/* + * zynq_nand_calculate_hwecc - Calculate Hardware ECC + * @mtd: Pointer to the mtd_info structure + * @data: Pointer to the page data + * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored + * + * This function retrieves the Hardware ECC data from the controller and returns + * ECC data back to the MTD subsystem. + * + * returns: 0 on success or error value on failure + */ +static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, + u8 *ecc_code) +{ + u32 ecc_value = 0; + u8 ecc_reg, ecc_byte; + u32 ecc_status; + + /* Wait till the ECC operation is complete */ + ecc_status = zynq_nand_waitfor_ecc_completion(); + if (ecc_status < 0) { + printf("%s: Timeout\n", __func__); + return ecc_status; + } + + for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) { + /* Read ECC value for each block */ + ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg); + ecc_status = (ecc_value >> 24) & 0xFF; + /* ECC value valid */ + if (ecc_status & 0x40) { + for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) { + /* Copy ECC bytes to MTD buffer */ + *ecc_code = ecc_value & 0xFF; + ecc_value = ecc_value >> 8; + ecc_code++; + } + } else { + debug("%s: ecc status failed\n", __func__); + } + } + return 0; +} + +/* + * onehot - onehot function + * @value: value to check for onehot + * + * This function checks whether a value is onehot or not. + * onehot is if and only if onebit is set. + * + */ +static int onehot(unsigned short value) +{ + return ((value & (value-1)) == 0); +} + +/* + * zynq_nand_correct_data - ECC correction function + * @mtd: Pointer to the mtd_info structure + * @buf: Pointer to the page data + * @read_ecc: Pointer to the ECC value read from spare data area + * @calc_ecc: Pointer to the calculated ECC value + * + * This function corrects the ECC single bit errors & detects 2-bit errors. + * + * returns: 0 if no ECC errors found + * 1 if single bit error found and corrected. + * -1 if multiple ECC errors found. + */ +static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf, + unsigned char *read_ecc, unsigned char *calc_ecc) +{ + unsigned char bit_addr; + unsigned int byte_addr; + unsigned short ecc_odd, ecc_even; + unsigned short read_ecc_lower, read_ecc_upper; + unsigned short calc_ecc_lower, calc_ecc_upper; + + read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff; + read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff; + + calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff; + calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff; + + ecc_odd = read_ecc_lower ^ calc_ecc_lower; + ecc_even = read_ecc_upper ^ calc_ecc_upper; + + if ((ecc_odd == 0) && (ecc_even == 0)) + return 0; /* no error */ + else if (ecc_odd == (~ecc_even & 0xfff)) { + /* bits [11:3] of error code is byte offset */ + byte_addr = (ecc_odd >> 3) & 0x1ff; + /* bits [2:0] of error code is bit offset */ + bit_addr = ecc_odd & 0x7; + /* Toggling error bit */ + buf[byte_addr] ^= (1 << bit_addr); + return 1; + } else if (onehot(ecc_odd | ecc_even) == 1) { + return 1; /* one error in parity */ + } else { + return -1; /* Uncorrectable error */ + } +} + +/* + * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to read + * @sndcmd: flag whether to issue read command or not + */ +static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + + p = chip->oob_poi; + chip->read_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->read_buf(mtd, p, data_width); + + return 0; +} + +/* + * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to write + */ +static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + const u8 *buf = chip->oob_poi; + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + + chip->write_buf(mtd, buf, (mtd->oobsize - data_width)); + buf += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + chip->write_buf(mtd, buf, data_width); + + /* Send command to program the OOB data */ + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + return status & NAND_STATUS_FAIL ? -EIO : 0; +} + +/* + * zynq_nand_read_page_raw - [Intern] read raw page data without ecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to read + */ +static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->read_buf(mtd, buf, mtd->writesize); + + p = chip->oob_poi; + chip->read_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + chip->read_buf(mtd, p, data_width); + return 0; +} + +static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + chip->read_buf(mtd, buf, mtd->writesize); + return 0; +} + +static int zynq_nand_read_subpage_raw(struct mtd_info *mtd, + struct nand_chip *chip, u32 data_offs, + u32 readlen, u8 *buf) +{ + if (data_offs != 0) { + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1); + buf += data_offs; + } + + chip->read_buf(mtd, buf, readlen); + return 0; +} + +/* + * zynq_nand_write_page_raw - [Intern] raw page write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + */ +static int zynq_nand_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->write_buf(mtd, buf, mtd->writesize); + + p = chip->oob_poi; + chip->write_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + + chip->write_buf(mtd, p, data_width); + + return 0; +} + +/* + * nand_write_page_hwecc - Hardware ECC based page write function + * @mtd: Pointer to the mtd info structure + * @chip: Pointer to the NAND chip info structure + * @buf: Pointer to the data buffer + * @oob_required: must write chip->oob_poi to OOB + * + * This functions writes data and hardware generated ECC values in to the page. + */ +static int zynq_nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + int i, eccsize = chip->ecc.size; + int eccsteps = chip->ecc.steps; + u8 *ecc_calc = chip->buffers->ecccalc; + const u8 *p = buf; + u32 *eccpos = chip->ecc.layout->eccpos; + unsigned long data_phase_addr = 0; + unsigned long data_width = 4; + u8 *oob_ptr; + + for (; (eccsteps - 1); eccsteps--) { + chip->write_buf(mtd, p, eccsize); + p += eccsize; + } + chip->write_buf(mtd, p, (eccsize - data_width)); + p += (eccsize - data_width); + + /* Set ECC Last bit to 1 */ + data_phase_addr = (unsigned long) chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + chip->write_buf(mtd, p, data_width); + + /* Wait for ECC to be calculated and read the error values */ + p = buf; + chip->ecc.calculate(mtd, p, &ecc_calc[0]); + + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]); + + /* Clear ECC last bit */ + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + + /* Write the spare area with ECC bytes */ + oob_ptr = chip->oob_poi; + chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + oob_ptr += (mtd->oobsize - data_width); + chip->write_buf(mtd, oob_ptr, data_width); + + return 0; +} + +/* + * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page + * write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + */ +static int zynq_nand_write_page_swecc(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *ecc_calc = chip->buffers->ecccalc; + const u8 *p = buf; + u32 *eccpos = chip->ecc.layout->eccpos; + + /* Software ecc calculation */ + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ecc_calc[i]; + + return chip->ecc.write_page_raw(mtd, chip, buf, 1); +} + +/* + * nand_read_page_hwecc - Hardware ECC based page read function + * @mtd: Pointer to the mtd info structure + * @chip: Pointer to the NAND chip info structure + * @buf: Pointer to the buffer to store read data + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to read + * + * This functions reads data and checks the data integrity by comparing hardware + * generated ECC values and read ECC values from spare area. + * + * returns: 0 always and updates ECC operation status in to MTD structure + */ +static int zynq_nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int i, stat, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *p = buf; + u8 *ecc_calc = chip->buffers->ecccalc; + u8 *ecc_code = chip->buffers->ecccode; + u32 *eccpos = chip->ecc.layout->eccpos; + unsigned long data_phase_addr = 0; + unsigned long data_width = 4; + u8 *oob_ptr; + + for (; (eccsteps - 1); eccsteps--) { + chip->read_buf(mtd, p, eccsize); + p += eccsize; + } + chip->read_buf(mtd, p, (eccsize - data_width)); + p += (eccsize - data_width); + + /* Set ECC Last bit to 1 */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->read_buf(mtd, p, data_width); + + /* Read the calculated ECC value */ + p = buf; + chip->ecc.calculate(mtd, p, &ecc_calc[0]); + + /* Clear ECC last bit */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + /* Read the stored ECC value */ + oob_ptr = chip->oob_poi; + chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); + + /* de-assert chip select */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + oob_ptr += (mtd->oobsize - data_width); + chip->read_buf(mtd, oob_ptr, data_width); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = ~(chip->oob_poi[eccpos[i]]); + + eccsteps = chip->ecc.steps; + p = buf; + + /* Check ECC error for all blocks and correct if it is correctable */ + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/* + * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page + * read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + */ +static int zynq_nand_read_page_swecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *p = buf; + u8 *ecc_calc = chip->buffers->ecccalc; + u8 *ecc_code = chip->buffers->ecccode; + u32 *eccpos = chip->ecc.layout->eccpos; + + chip->ecc.read_page_raw(mtd, chip, buf, 1, page); + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + eccsteps = chip->ecc.steps; + p = buf; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/* + * zynq_nand_select_chip - Select the flash device + * @mtd: Pointer to the mtd_info structure + * @chip: Chip number to be selected + * + * This function is empty as the NAND controller handles chip select line + * internally based on the chip address passed in command and data phase. + */ +static void zynq_nand_select_chip(struct mtd_info *mtd, int chip) +{ + return; +} + +/* + * zynq_nand_cmd_function - Send command to NAND device + * @mtd: Pointer to the mtd_info structure + * @command: The command to be sent to the flash device + * @column: The column address for this command, -1 if none + * @page_addr: The page address for this command, -1 if none + */ +static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd->priv; + const struct zynq_nand_command_format *curr_cmd = NULL; + struct zynq_nand_info *xnand; + void *cmd_addr; + unsigned long cmd_data = 0; + unsigned long cmd_phase_addr = 0; + unsigned long data_phase_addr = 0; + unsigned long end_cmd = 0; + unsigned long end_cmd_valid = 0; + unsigned long i; + + xnand = (struct zynq_nand_info *)chip->priv; + if (xnand->end_cmd_pending) { + /* Check for end command if this command request is same as the + * pending command then return + */ + if (xnand->end_cmd == command) { + xnand->end_cmd = 0; + xnand->end_cmd_pending = 0; + return; + } + } + + /* Emulate NAND_CMD_READOOB for large page device */ + if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) && + (command == NAND_CMD_READOOB)) { + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Get the command format */ + for (i = 0; (zynq_nand_commands[i].start_cmd != NAND_CMD_NONE || + zynq_nand_commands[i].end_cmd != NAND_CMD_NONE); i++) { + if (command == zynq_nand_commands[i].start_cmd) + curr_cmd = &zynq_nand_commands[i]; + } + if (curr_cmd == NULL) + return; + + /* Clear interrupt */ + writel((1 << 4), &zynq_nand_smc_base->cfr); + + /* Get the command phase address */ + if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) + end_cmd_valid = 1; + + if (curr_cmd->end_cmd == NAND_CMD_NONE) + end_cmd = 0x0; + else + end_cmd = curr_cmd->end_cmd; + + cmd_phase_addr = (unsigned long)xnand->nand_base | + (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) | + (end_cmd_valid << END_CMD_VALID_SHIFT) | + (COMMAND_PHASE) | + (end_cmd << END_CMD_SHIFT) | + (curr_cmd->start_cmd << START_CMD_SHIFT); + + cmd_addr = (void __iomem *)cmd_phase_addr; + + /* Get the data phase address */ + end_cmd_valid = 0; + + data_phase_addr = (unsigned long)xnand->nand_base | + (0x0 << CLEAR_CS_SHIFT) | + (end_cmd_valid << END_CMD_VALID_SHIFT) | + (DATA_PHASE) | + (end_cmd << END_CMD_SHIFT) | + (0x0 << ECC_LAST_SHIFT); + + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->IO_ADDR_W = chip->IO_ADDR_R; + + /* Command phase AXI Read & Write */ + if (column != -1 && page_addr != -1) { + /* Adjust columns for 16 bit bus width */ + if (chip->options & NAND_BUSWIDTH_16) + column >>= 1; + cmd_data = column; + if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) { + cmd_data |= page_addr << 16; + /* Another address cycle for devices > 128MiB */ + if (chip->chipsize > (128 << 20)) { + writel(cmd_data, cmd_addr); + cmd_data = (page_addr >> 16); + } + } else { + cmd_data |= page_addr << 8; + } + } + /* Erase */ + else if (page_addr != -1) + cmd_data = page_addr; + /* Change read/write column, read id etc */ + else if (column != -1) { + /* Adjust columns for 16 bit bus width */ + if ((chip->options & NAND_BUSWIDTH_16) && + ((command == NAND_CMD_READ0) || + (command == NAND_CMD_SEQIN) || + (command == NAND_CMD_RNDOUT) || + (command == NAND_CMD_RNDIN))) + column >>= 1; + cmd_data = column; + } else + ; + + writel(cmd_data, cmd_addr); + + if (curr_cmd->end_cmd_valid) { + xnand->end_cmd = curr_cmd->end_cmd; + xnand->end_cmd_pending = 1; + } + + ndelay(100); + + if ((command == NAND_CMD_READ0) || + (command == NAND_CMD_RESET) || + (command == NAND_CMD_PARAM) || + (command == NAND_CMD_GET_FEATURES)) { + while (!chip->dev_ready(mtd)) + ; + return; + } +} + +/* + * zynq_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_R; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + *buf = readb(nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + *(u32 *)buf = readl(nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + + if (len) + *buf = readb(nand); + } +} + +/* + * zynq_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_W; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + writeb(*buf, nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + writel(*(u32 *)buf, nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + + if (len) + writeb(*buf, nand); + } +} + +/* + * zynq_nand_device_ready - Check device ready/busy line + * @mtd: Pointer to the mtd_info structure + * + * returns: 0 on busy or 1 on ready state + */ +static int zynq_nand_device_ready(struct mtd_info *mtd) +{ + /* Check the raw_int_status1 bit */ + if ((readl(&zynq_nand_smc_base->csr)) & 0x40) { + /* Clear the interrupt condition */ + writel((1 << 4), &zynq_nand_smc_base->cfr); + return 1; + } + return 0; +} + +/* + * zynq_nand_check_is_16bit_bw_flash - checking for 16 or 8 bit buswidth nand + * + * This function will check nand buswidth whether it supports 16 or 8 bit + * based on the MIO configuration done by FSBL. + * + * User needs to correctly configure the MIO's based on the + * buswidth supported by the nand flash which is present on the board. + * + * function will return -1, if there is no MIO configuration for + * nand flash. + */ +static int zynq_nand_check_is_16bit_bw_flash(void) +{ + int is_16bit_bw = NAND_BW_UNKNOWN; + int mio_num_8bit = 0, mio_num_16bit = 0; + + mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8"); + if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) + is_16bit_bw = NAND_BW_8BIT; + + mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16"); + if ((mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) && + (mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)) + is_16bit_bw = NAND_BW_16BIT; + + return is_16bit_bw; +} + +static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +{ + struct zynq_nand_info *xnand; + struct mtd_info *mtd; + unsigned long ecc_page_size; + int err = -1; + u8 maf_id, dev_id, i; + u8 get_feature[4]; + u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00}; + unsigned long ecc_cfg; + int ondie_ecc_enabled = 0; + int is_16bit_bw; + + xnand = calloc(1, sizeof(struct zynq_nand_info)); + if (!xnand) { + printf("%s: failed to allocate\n", __func__); + goto free; + } + + xnand->nand_base = (void *)ZYNQ_NAND_BASEADDR; + mtd = &nand_info[0]; + + nand_chip->priv = xnand; + mtd->priv = nand_chip; + + /* Set address of NAND IO lines */ + nand_chip->IO_ADDR_R = xnand->nand_base; + nand_chip->IO_ADDR_W = xnand->nand_base; + + /* Set the driver entry points for MTD */ + nand_chip->cmdfunc = zynq_nand_cmd_function; + nand_chip->dev_ready = zynq_nand_device_ready; + nand_chip->select_chip = zynq_nand_select_chip; + + /* If we don't set this delay driver sets 20us by default */ + nand_chip->chip_delay = 30; + + /* Buffer read/write routines */ + nand_chip->read_buf = zynq_nand_read_buf; + nand_chip->write_buf = zynq_nand_write_buf; + + /* Check the NAND buswidth */ + /* FIXME this will be changed by using NAND_BUSWIDTH_AUTO */ + is_16bit_bw = zynq_nand_check_is_16bit_bw_flash(); + if (is_16bit_bw == NAND_BW_UNKNOWN) { + printf("%s: Unable detect NAND based on MIO settings\n", + __func__); + goto free; + } else if (is_16bit_bw == NAND_BW_16BIT) { + nand_chip->options = NAND_BUSWIDTH_16; + } + nand_chip->bbt_options = NAND_BBT_USE_FLASH; + + /* Initialize the NAND flash interface on NAND controller */ + if (zynq_nand_init_nand_flash(nand_chip->options) < 0) { + printf("%s: nand flash init failed\n", __func__); + goto free; + } + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, 1, NULL)) { + printf("%s: nand_scan_ident failed\n", __func__); + goto fail; + } + + /* Send the command for reading device ID */ + nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + maf_id = nand_chip->read_byte(mtd); + dev_id = nand_chip->read_byte(mtd); + + if ((maf_id == 0x2c) && ((dev_id == 0xf1) || + (dev_id == 0xa1) || (dev_id == 0xb1) || + (dev_id == 0xaa) || (dev_id == 0xba) || + (dev_id == 0xda) || (dev_id == 0xca) || + (dev_id == 0xac) || (dev_id == 0xbc) || + (dev_id == 0xdc) || (dev_id == 0xcc) || + (dev_id == 0xa3) || (dev_id == 0xb3) || + (dev_id == 0xd3) || (dev_id == 0xc3))) { + nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + + for (i = 0; i < 4; i++) + writeb(set_feature[i], nand_chip->IO_ADDR_W); + + /* wait for 1us after writing data with SET_FEATURES command */ + ndelay(1000); + + nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + nand_chip->read_buf(mtd, get_feature, 4); + + if (get_feature[0] & 0x08) { + debug("%s: OnDie ECC flash\n", __func__); + ondie_ecc_enabled = 1; + } else { + printf("%s: Unable to detect OnDie ECC\n", __func__); + } + } + + if (ondie_ecc_enabled) { + /* bypass the controller ECC block */ + ecc_cfg = readl(&zynq_nand_smc_base->emcr); + ecc_cfg &= ~0xc; + writel(ecc_cfg, &zynq_nand_smc_base->emcr); + + /* The software ECC routines won't work + * with the SMC controller + */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.strength = 1; + nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob; + nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw; + nand_chip->ecc.write_page = zynq_nand_write_page_raw; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + nand_chip->ecc.size = mtd->writesize; + nand_chip->ecc.bytes = 0; + + /* NAND with on-die ECC supports subpage reads */ + nand_chip->options |= NAND_SUBPAGE_READ; + + /* On-Die ECC spare bytes offset 8 is used for ECC codes */ + if (ondie_ecc_enabled) { + nand_chip->ecc.layout = &ondie_nand_oob_64; + /* Use the BBT pattern descriptors */ + nand_chip->bbt_td = &bbt_main_descr; + nand_chip->bbt_md = &bbt_mirror_descr; + } + } else { + /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.strength = 1; + nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE; + nand_chip->ecc.bytes = 3; + nand_chip->ecc.calculate = zynq_nand_calculate_hwecc; + nand_chip->ecc.correct = zynq_nand_correct_data; + nand_chip->ecc.hwctl = NULL; + nand_chip->ecc.read_page = zynq_nand_read_page_hwecc; + nand_chip->ecc.write_page = zynq_nand_write_page_hwecc; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + + switch (mtd->writesize) { + case 512: + ecc_page_size = 0x1; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + case 1024: + ecc_page_size = 0x2; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + case 2048: + ecc_page_size = 0x3; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + default: + /* The software ECC routines won't work with + * the SMC controller + */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.calculate = nand_calculate_ecc; + nand_chip->ecc.correct = nand_correct_data; + nand_chip->ecc.read_page = zynq_nand_read_page_swecc; + /* nand_chip->ecc.read_subpage = nand_read_subpage; */ + nand_chip->ecc.write_page = zynq_nand_write_page_swecc; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = + zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + nand_chip->ecc.size = 256; + nand_chip->ecc.bytes = 3; + break; + } + + if (mtd->oobsize == 16) + nand_chip->ecc.layout = &nand_oob_16; + else if (mtd->oobsize == 64) + nand_chip->ecc.layout = &nand_oob_64; + else + ; + } + + /* second phase scan */ + if (nand_scan_tail(mtd)) { + printf("%s: nand_scan_tailfailed\n", __func__); + goto fail; + } + + if (nand_register(devnum)) + goto fail; + + return 0; +fail: + nand_release(mtd); +free: + kfree(xnand); + return err; +} + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +void board_nand_init(void) +{ + struct nand_chip *nand = &nand_chip[0]; + + if (zynq_nand_init(nand, 0)) + puts("ZYNQ NAND init failed\n"); +} diff --cc drivers/mtd/spi/sf_internal.h index 869aa49d8ef,732ddf836df..6439d6acd02 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@@ -22,45 -28,17 +28,45 @@@ #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 -#define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_WRITE_ENABLE 0x06 +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_32K 0x52 +#define CMD_ERASE_64K 0xd8 +#define CMD_ERASE_CHIP 0xc7 + +/* Write commands */ +#define CMD_QUAD_PAGE_PROGRAM 0x32 + +static const u32 spi_write_cmds_array[] = { + CMD_PAGE_PROGRAM, + CMD_QUAD_PAGE_PROGRAM, +}; + +/* Read commands */ +#define CMD_READ_ARRAY_SLOW 0x03 +#define CMD_READ_DUAL_OUTPUT_FAST 0x3b +#define CMD_READ_DUAL_IO_FAST 0xbb +#define CMD_READ_QUAD_OUTPUT_FAST 0x6b + +static const u32 spi_read_cmds_array[] = { + CMD_READ_ARRAY_SLOW, + CMD_READ_ARRAY_FAST, + CMD_READ_DUAL_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, + CMD_READ_QUAD_OUTPUT_FAST, +}; + +#define SPI_FLASH_16MB_BOUN 0x1000000 - /* Manufacture ID's */ - #define SPI_FLASH_SPANSION_IDCODE0 0x01 - #define SPI_FLASH_STMICRO_IDCODE0 0x20 - #define SPI_FLASH_WINBOND_IDCODE0 0xef + /* Read commands */ + #define CMD_READ_ARRAY_SLOW 0x03 + #define CMD_READ_ARRAY_FAST 0x0b + #define CMD_READ_ID 0x9f - #ifdef CONFIG_SPI_FLASH_BAR /* Bank addr access commands */ + #ifdef CONFIG_SPI_FLASH_BAR # define CMD_BANKADDR_BRWR 0x17 # define CMD_BANKADDR_BRRD 0x16 # define CMD_EXTNADDR_WREAR 0xC5 @@@ -69,9 -47,23 +75,24 @@@ /* Common status */ #define STATUS_WIP 0x01 +#define STATUS_QEB 0x02 #define STATUS_PEC 0x80 + /* Flash timeout values */ + #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) + #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) + #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) + + /* SST specific */ + #ifdef CONFIG_SPI_FLASH_SST + # define SST_WP 0x01 /* Supports AAI word program */ + # define CMD_SST_BP 0x02 /* Byte Program */ + # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ + + int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); + #endif + /* Send a single-byte command to the device and read the response */ int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); @@@ -115,26 -103,12 +132,23 @@@ static inline int spi_flash_cmd_write_d return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); } +/* Program the status register. */ +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); + +/* Program the config register */ +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr); + +#ifdef CONFIG_SPI_FLASH_BAR - /* Program the bank address register */ - int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel); - +/* Configure the BAR - discover the bank cmds */ +int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0); +#endif + /* - * Same as spi_flash_cmd_read() except it also claims/releases the SPI - * bus. Used as common part of the ->read() operation. + * Send the read status command to the device and wait for the wip + * (write-in-progress) bit to clear itself. */ - int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len); + int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); + /* * Used for spi_flash write operation * - SPI claim diff --cc drivers/net/xilinx_ll_temac.c index 5f8fc9ce177,dab78d073da..5ef09542e52 --- a/drivers/net/xilinx_ll_temac.c +++ b/drivers/net/xilinx_ll_temac.c @@@ -8,10 -11,12 +8,7 @@@ * Copyright (C) 2008 Nissin Systems Co.,Ltd. * March 2008 created * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * SPDX-License-Identifier: GPL-2.0+ - * - * [0]: http://www.xilinx.com/support/documentation - * - * [S]: [0]/ip_documentation/xps_ll_temac.pdf - * [A]: [0]/application_notes/xapp1041.pdf */ #include diff --cc drivers/spi/Makefile index 558fd33e5cc,e5941b09f61..37c3d04a58c --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@@ -54,9 -38,9 +38,10 @@@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi. COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o + COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o +COBJS-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --cc drivers/spi/zynq_qspi.c index 2fa984d3bfb,00000000000..89f028e168f mode 100644,000000..100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@@ -1,1000 -1,0 +1,993 @@@ +/* + * (C) Copyright 2011 - 2013 Xilinx + * + * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only) + * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place, Suite 330, Boston, MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* QSPI Transmit Data Register */ +#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */ +#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */ +#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */ +#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */ + +/* + * QSPI Configuration Register bit Masks + * + * This register contains various control bits that effect the operation + * of the QSPI controller + */ +#define ZYNQ_QSPI_CONFIG_IFMODE_MASK (1 << 31) /* Flash intrface mode*/ +#define ZYNQ_QSPI_CONFIG_HOLDB_MASK (1 << 19) /* Holdb Mask */ +#define ZYNQ_QSPI_CONFIG_MSA_MASK (1 << 15) /* Manual start enb */ +#define ZYNQ_QSPI_CONFIG_MCS_MASK (1 << 14) /* Manual chip select */ +#define ZYNQ_QSPI_CONFIG_PCS_MASK (1 << 10) /* Peri chip select */ +#define ZYNQ_QSPI_CONFIG_REFCLK_MASK (1 << 8) /* Ref Clock Mask */ +#define ZYNQ_QSPI_CONFIG_FW_MASK (0x3 << 6) /* FIFO width */ +#define ZYNQ_QSPI_CONFIG_BAUDRATE_MASK (0x7 << 3) /* Baudrate Divisor Mask */ +#define ZYNQ_QSPI_CONFIG_MSTREN_MASK (1 << 0) /* Mode select */ +#define ZYNQ_QSPI_CONFIG_MANSRT_MASK 0x00010000 /* Manual TX Start */ +#define ZYNQ_QSPI_CONFIG_CPHA_MASK 0x00000004 /* Clock Phase Control */ +#define ZYNQ_QSPI_CONFIG_CPOL_MASK 0x00000002 /* Clock Polarity Control */ +#define ZYNQ_QSPI_CONFIG_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */ +#define ZYNQ_QSPI_CONFIG_CLR_ALL_MASK (ZYNQ_QSPI_CONFIG_IFMODE_MASK | \ + ZYNQ_QSPI_CONFIG_HOLDB_MASK | \ + ZYNQ_QSPI_CONFIG_MANSRT_MASK | \ + ZYNQ_QSPI_CONFIG_MSA_MASK | \ + ZYNQ_QSPI_CONFIG_MCS_MASK | \ + ZYNQ_QSPI_CONFIG_PCS_MASK | \ + ZYNQ_QSPI_CONFIG_REFCLK_MASK | \ + ZYNQ_QSPI_CONFIG_FW_MASK | \ + ZYNQ_QSPI_CONFIG_BAUDRATE_MASK | \ + ZYNQ_QSPI_CONFIG_CPHA_MASK | \ + ZYNQ_QSPI_CONFIG_CPOL_MASK | \ + ZYNQ_QSPI_CONFIG_MSTREN_MASK) + +/* + * QSPI Interrupt Registers bit Masks + * + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same + * bit definitions. + */ +#define ZYNQ_QSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */ +#define ZYNQ_QSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */ +#define ZYNQ_QSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */ +#define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \ + ZYNQ_QSPI_IXR_RXNEMTY_MASK) + +/* + * QSPI Enable Register bit Masks + * + * This register is used to enable or disable the QSPI controller + */ +#define ZYNQ_QSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */ + +/* + * QSPI Linear Configuration Register + * + * It is named Linear Configuration but it controls other modes when not in + * linear mode also. + */ +#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK 0x40000000 /* QSPI Enable Bit Mask */ +#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK 0x20000000 /* QSPI Enable Bit Mask */ +#define ZYNQ_QSPI_LCFG_U_PAGE 0x10000000 /* QSPI Upper memory set */ + +#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8 + +#define ZYNQ_QSPI_FR_QOUT_CODE 0x6B /* read instruction code */ + +/* + * The modebits configurable by the driver to make the SPI support different + * data formats + */ +#define MODEBITS (SPI_CPOL | SPI_CPHA) + +/* Definitions for the status of queue */ +#define ZYNQ_QSPI_QUEUE_STOPPED 0 +#define ZYNQ_QSPI_QUEUE_RUNNING 1 + +/* QSPI MIO's count for different connection topologies */ +#define ZYNQ_QSPI_MIO_NUM_QSPI0 6 +#define ZYNQ_QSPI_MIO_NUM_QSPI1 5 +#define ZYNQ_QSPI_MIO_NUM_QSPI1_CS 1 + +/* Definitions of the flash commands - Flash opcodes in ascending order */ +#define ZYNQ_QSPI_FLASH_OPCODE_WRSR 0x01 /* Write status register */ +#define ZYNQ_QSPI_FLASH_OPCODE_PP 0x02 /* Page program */ +#define ZYNQ_QSPI_FLASH_OPCODE_NR 0x03 /* Normal read data bytes */ +#define ZYNQ_QSPI_FLASH_OPCODE_WRDS 0x04 /* Write disable */ +#define ZYNQ_QSPI_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */ +#define ZYNQ_QSPI_FLASH_OPCODE_WREN 0x06 /* Write enable */ +#define ZYNQ_QSPI_FLASH_OPCODE_FR 0x0B /* Fast read data bytes */ +#define ZYNQ_QSPI_FLASH_OPCODE_BRRD 0x16 /* Bank address reg read */ +#define ZYNQ_QSPI_FLASH_OPCODE_BRWR 0x17 /* Bank address reg write */ +#define ZYNQ_QSPI_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */ +#define ZYNQ_QSPI_FLASH_OPCODE_QPP 0x32 /* Quad Page Program */ +#define ZYNQ_QSPI_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */ +#define ZYNQ_QSPI_FLASH_OPCODE_DR 0x3B /* Dual read data bytes */ +#define ZYNQ_QSPI_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */ +#define ZYNQ_QSPI_FLASH_OPCODE_QR 0x6B /* Quad read data bytes */ +#define ZYNQ_QSPI_FLASH_OPCODE_ES 0x75 /* Erase suspend */ +#define ZYNQ_QSPI_FLASH_OPCODE_ER 0x7A /* Erase resume */ +#define ZYNQ_QSPI_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */ +#define ZYNQ_QSPI_FLASH_OPCODE_DIOR 0xBB /* Dual IO high perf read */ +#define ZYNQ_QSPI_FLASH_OPCODE_WREAR 0xC5 /* Extended address reg write */ +#define ZYNQ_QSPI_FLASH_OPCODE_RDEAR 0xC8 /* Extended address reg read */ +#define ZYNQ_QSPI_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */ +#define ZYNQ_QSPI_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/ + +/* QSPI register offsets */ +struct zynq_qspi_regs { + u32 confr; /* 0x00 */ + u32 isr; /* 0x04 */ + u32 ier; /* 0x08 */ + u32 idisr; /* 0x0C */ + u32 imaskr; /* 0x10 */ + u32 enbr; /* 0x14 */ + u32 dr; /* 0x18 */ + u32 txd0r; /* 0x1C */ + u32 drxr; /* 0x20 */ + u32 sicr; /* 0x24 */ + u32 txftr; /* 0x28 */ + u32 rxftr; /* 0x2C */ + u32 gpior; /* 0x30 */ + u32 reserved0[19]; + u32 txd1r; /* 0x80 */ + u32 txd2r; /* 0x84 */ + u32 txd3r; /* 0x88 */ + u32 reserved1[5]; + u32 lcr; /* 0xA0 */ + u32 reserved2[22]; + u32 midr; /* 0xFC */ +}; + +#define zynq_qspi_base ((struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR) + +struct zynq_qspi { + u32 input_clk_hz; + u32 speed_hz; + const void *txbuf; + void *rxbuf; + int bytes_to_transfer; + int bytes_to_receive; + struct zynq_qspi_inst_format *curr_inst; + u8 inst_response; + unsigned int is_inst; + unsigned int is_dual; + unsigned int u_page; +}; + +struct spi_device { + struct zynq_qspi master; + u32 max_speed_hz; + u8 chip_select; + u8 mode; + u8 bits_per_word; +}; + +struct spi_transfer { + const void *tx_buf; + void *rx_buf; + unsigned len; + unsigned cs_change:1; + u8 bits_per_word; + u16 delay_usecs; + u32 speed_hz; +}; + +struct zynq_qspi_slave { + struct spi_slave slave; + struct spi_device qspi; +}; +#define to_zynq_qspi_slave(s) container_of(s, struct zynq_qspi_slave, slave) + +/* + * struct zynq_qspi_inst_format - Defines qspi flash instruction format + * @opcode: Operational code of instruction + * @inst_size: Size of the instruction including address bytes + * @offset: Register address where instruction has to be written + */ +struct zynq_qspi_inst_format { + u8 opcode; + u8 inst_size; + u8 offset; +}; + +/* List of all the QSPI instructions and its format */ +static struct zynq_qspi_inst_format flash_inst[] = { + { ZYNQ_QSPI_FLASH_OPCODE_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_BE, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_ES, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_ER, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_NR, 4, ZYNQ_QSPI_TXD_00_00_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_FR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_DR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_QR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_BRWR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_BRRD, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_WREAR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_RDEAR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_QPP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET }, + { ZYNQ_QSPI_FLASH_OPCODE_DIOR, 4, ZYNQ_QSPI_TXD_00_00_OFFSET }, + /* Add all the instructions supported by the flash device */ +}; + +/* + * zynq_qspi_init_hw - Initialize the hardware + * @is_dual: Indicates whether dual memories are used + * @cs: Indicates which chip select is used in dual stacked + * + * The default settings of the QSPI controller's configurable parameters on + * reset are + * - Master mode + * - Baud rate divisor is set to 2 + * - Threshold value for TX FIFO not full interrupt is set to 1 + * - Flash memory interface mode enabled + * - Size of the word to be transferred as 8 bit + * This function performs the following actions + * - Disable and clear all the interrupts + * - Enable manual slave select + * - Enable manual start + * - Deselect all the chip select lines + * - Set the size of the word to be transferred as 32 bit + * - Set the little endian mode of TX FIFO and + * - Enable the QSPI controller + */ +static void zynq_qspi_init_hw(int is_dual, unsigned int cs) +{ + u32 config_reg; + + writel(~ZYNQ_QSPI_ENABLE_ENABLE_MASK, &zynq_qspi_base->enbr); + writel(0x7F, &zynq_qspi_base->idisr); + + /* Disable linear mode as the boot loader may have used it */ + writel(0x0, &zynq_qspi_base->lcr); + + /* Clear the TX and RX threshold reg */ + writel(0x1, &zynq_qspi_base->txftr); + writel(0x1, &zynq_qspi_base->rxftr); + + /* Clear the RX FIFO */ + while (readl(&zynq_qspi_base->isr) & ZYNQ_QSPI_IXR_RXNEMTY_MASK) + readl(&zynq_qspi_base->drxr); + + writel(0x7F, &zynq_qspi_base->isr); + config_reg = readl(&zynq_qspi_base->confr); + /* Clear all the bits before setting required configuration */ + config_reg &= ~ZYNQ_QSPI_CONFIG_CLR_ALL_MASK; + config_reg |= ZYNQ_QSPI_CONFIG_IFMODE_MASK | + ZYNQ_QSPI_CONFIG_MSA_MASK | ZYNQ_QSPI_CONFIG_MCS_MASK | + ZYNQ_QSPI_CONFIG_PCS_MASK | ZYNQ_QSPI_CONFIG_FW_MASK | + ZYNQ_QSPI_CONFIG_MSTREN_MASK; + if (is_dual == MODE_DUAL_STACKED) + config_reg |= 0x10; + writel(config_reg, &zynq_qspi_base->confr); + + if (is_dual == MODE_DUAL_PARALLEL) + /* Enable two memories on seperate buses */ + writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | + ZYNQ_QSPI_LCFG_SEP_BUS_MASK | + (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | + ZYNQ_QSPI_FR_QOUT_CODE), + &zynq_qspi_base->lcr); + else if (is_dual == MODE_DUAL_STACKED) + /* Configure two memories on shared bus by enabling lower mem */ + writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | + (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | + ZYNQ_QSPI_FR_QOUT_CODE), + &zynq_qspi_base->lcr); + + writel(ZYNQ_QSPI_ENABLE_ENABLE_MASK, &zynq_qspi_base->enbr); +} + +/* + * zynq_qspi_copy_read_data - Copy data to RX buffer + * @zqspi: Pointer to the zynq_qspi structure + * @data: The 32 bit variable where data is stored + * @size: Number of bytes to be copied from data to RX buffer + */ +static void zynq_qspi_copy_read_data(struct zynq_qspi *zqspi, u32 data, u8 size) +{ + u8 byte3; + + debug("%s: data 0x%04x rxbuf addr: 0x%08x size %d\n", __func__ , + data, (unsigned)(zqspi->rxbuf), size); + + if (zqspi->rxbuf) { + switch (size) { + case 1: + *((u8 *)zqspi->rxbuf) = data; + zqspi->rxbuf += 1; + break; + case 2: + *((u16 *)zqspi->rxbuf) = data; + zqspi->rxbuf += 2; + break; + case 3: + *((u16 *)zqspi->rxbuf) = data; + zqspi->rxbuf += 2; + byte3 = (u8)(data >> 16); + *((u8 *)zqspi->rxbuf) = byte3; + zqspi->rxbuf += 1; + break; + case 4: + /* Can not assume word aligned buffer */ + memcpy(zqspi->rxbuf, &data, size); + zqspi->rxbuf += 4; + break; + default: + /* This will never execute */ + break; + } + } + zqspi->bytes_to_receive -= size; + if (zqspi->bytes_to_receive < 0) + zqspi->bytes_to_receive = 0; +} + +/* + * zynq_qspi_copy_write_data - Copy data from TX buffer + * @zqspi: Pointer to the zynq_qspi structure + * @data: Pointer to the 32 bit variable where data is to be copied + * @size: Number of bytes to be copied from TX buffer to data + */ +static void zynq_qspi_copy_write_data(struct zynq_qspi *zqspi, + u32 *data, u8 size) +{ + if (zqspi->txbuf) { + switch (size) { + case 1: + *data = *((u8 *)zqspi->txbuf); + zqspi->txbuf += 1; + *data |= 0xFFFFFF00; + break; + case 2: + *data = *((u16 *)zqspi->txbuf); + zqspi->txbuf += 2; + *data |= 0xFFFF0000; + break; + case 3: + *data = *((u16 *)zqspi->txbuf); + zqspi->txbuf += 2; + *data |= (*((u8 *)zqspi->txbuf) << 16); + zqspi->txbuf += 1; + *data |= 0xFF000000; + break; + case 4: + /* Can not assume word aligned buffer */ + memcpy(data, zqspi->txbuf, size); + zqspi->txbuf += 4; + break; + default: + /* This will never execute */ + break; + } + } else { + *data = 0; + } + + debug("%s: data 0x%08x txbuf addr: 0x%08x size %d\n", __func__, + *data, (u32)zqspi->txbuf, size); + + zqspi->bytes_to_transfer -= size; + if (zqspi->bytes_to_transfer < 0) + zqspi->bytes_to_transfer = 0; +} + +/* + * zynq_qspi_chipselect - Select or deselect the chip select line + * @qspi: Pointer to the spi_device structure + * @is_on: Select(1) or deselect (0) the chip select line + */ +static void zynq_qspi_chipselect(struct spi_device *qspi, int is_on) +{ + u32 config_reg; + + debug("%s: is_on: %d\n", __func__, is_on); + + config_reg = readl(&zynq_qspi_base->confr); + + if (is_on) { + /* Select the slave */ + config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK; + config_reg |= (((~(0x0001 << qspi->chip_select)) << 10) & + ZYNQ_QSPI_CONFIG_SSCTRL_MASK); + } else + /* Deselect the slave */ + config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK; + + writel(config_reg, &zynq_qspi_base->confr); +} + +/* + * zynq_qspi_setup_transfer - Configure QSPI controller for specified transfer + * @qspi: Pointer to the spi_device structure + * @transfer: Pointer to the spi_transfer structure which provides information + * about next transfer setup parameters + * + * Sets the operational mode of QSPI controller for the next QSPI transfer and + * sets the requested clock frequency. + * + * returns: 0 on success and -1 on invalid input parameter + * + * Note: If the requested frequency is not an exact match with what can be + * obtained using the prescalar value, the driver sets the clock frequency which + * is lower than the requested frequency (maximum lower) for the transfer. If + * the requested frequency is higher or lower than that is supported by the QSPI + * controller the driver will set the highest or lowest frequency supported by + * controller. + */ +static int zynq_qspi_setup_transfer(struct spi_device *qspi, + struct spi_transfer *transfer) +{ + struct zynq_qspi *zqspi = &qspi->master; + u8 bits_per_word; + u32 config_reg; + u32 req_hz; + u32 baud_rate_val = 0; + + debug("%s: qspi: 0x%08x transfer: 0x%08x\n", __func__, + (u32)qspi, (u32)transfer); + + bits_per_word = (transfer) ? + transfer->bits_per_word : qspi->bits_per_word; + req_hz = (transfer) ? transfer->speed_hz : qspi->max_speed_hz; + + if (qspi->mode & ~MODEBITS) { + printf("%s: Unsupported mode bits %x\n", + __func__, qspi->mode & ~MODEBITS); + return -1; + } + + if (bits_per_word != 32) + bits_per_word = 32; + + config_reg = readl(&zynq_qspi_base->confr); + + /* Set the QSPI clock phase and clock polarity */ + config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) & + (~ZYNQ_QSPI_CONFIG_CPOL_MASK); + if (qspi->mode & SPI_CPHA) + config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK; + if (qspi->mode & SPI_CPOL) + config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK; + + /* Set the clock frequency */ + if (zqspi->speed_hz != req_hz) { + baud_rate_val = 0; + while ((baud_rate_val < 8) && + (zqspi->input_clk_hz / (2 << baud_rate_val)) > req_hz) { + baud_rate_val++; + } + config_reg &= 0xFFFFFFC7; + config_reg |= (baud_rate_val << 3); + zqspi->speed_hz = req_hz; + } + + writel(config_reg, &zynq_qspi_base->confr); + + debug("%s: mode %d, %u bits/w, %u clock speed\n", __func__, + qspi->mode & MODEBITS, qspi->bits_per_word, zqspi->speed_hz); + + return 0; +} + +/* + * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible + * @zqspi: Pointer to the zynq_qspi structure + */ +static void zynq_qspi_fill_tx_fifo(struct zynq_qspi *zqspi) +{ + u32 data = 0; + unsigned len, offset; + static const unsigned offsets[4] = { + ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET, + ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET }; + + while ((!(readl(&zynq_qspi_base->isr) & + ZYNQ_QSPI_IXR_TXFULL_MASK)) && + (zqspi->bytes_to_transfer > 0)) { + if (zqspi->bytes_to_transfer < 4) { + /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */ + if (!(readl(&zynq_qspi_base->isr) + & ZYNQ_QSPI_IXR_TXNFULL_MASK) && + !zqspi->rxbuf) + return; + len = zqspi->bytes_to_transfer; + zynq_qspi_copy_write_data(zqspi, &data, len); + offset = (zqspi->rxbuf) ? offsets[0] : offsets[len]; + writel(data, &zynq_qspi_base->confr + (offset / 4)); + } else { + zynq_qspi_copy_write_data(zqspi, &data, 4); + writel(data, &zynq_qspi_base->txd0r); + } + } +} + +/* + * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller + * @zqspi: Pointer to the zynq_qspi structure + * + * This function handles TX empty and Mode Fault interrupts only. + * On TX empty interrupt this function reads the received data from RX FIFO and + * fills the TX FIFO if there is any data remaining to be transferred. + * On Mode Fault interrupt this function indicates that transfer is completed, + * the SPI subsystem will identify the error as the remaining bytes to be + * transferred is non-zero. + * + * returns: 0 for poll timeout + * 1 transfer operation complete + */ +static int zynq_qspi_irq_poll(struct zynq_qspi *zqspi) +{ + int max_loop; + u32 intr_status; + + debug("%s: zqspi: 0x%08x\n", __func__, (u32)zqspi); + + /* Poll until any of the interrupt status bits are set */ + max_loop = 0; + do { + intr_status = readl(&zynq_qspi_base->isr); + max_loop++; + } while ((intr_status == 0) && (max_loop < 100000)); + + if (intr_status == 0) { + printf("%s: Timeout\n", __func__); + return 0; + } + + writel(intr_status, &zynq_qspi_base->isr); + + /* Disable all interrupts */ + writel(ZYNQ_QSPI_IXR_ALL_MASK, &zynq_qspi_base->idisr); + if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) || + (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) { + /* + * This bit is set when Tx FIFO has < THRESHOLD entries. We have + * the THRESHOLD value set to 1, so this bit indicates Tx FIFO + * is empty + */ + u32 config_reg; + while (!(readl(&zynq_qspi_base->isr) & + ZYNQ_QSPI_IXR_TXNFULL_MASK) || + (readl(&zynq_qspi_base->isr) & + ZYNQ_QSPI_IXR_RXNEMTY_MASK)) { + /* Read out the data from the RX FIFO */ + while (readl(&zynq_qspi_base->isr) & + ZYNQ_QSPI_IXR_RXNEMTY_MASK) { + u32 data; + + data = readl(&zynq_qspi_base->drxr); + + if ((zqspi->inst_response) && + (!((zqspi->curr_inst->opcode == + ZYNQ_QSPI_FLASH_OPCODE_RDSR1) || + (zqspi->curr_inst->opcode == + ZYNQ_QSPI_FLASH_OPCODE_RDSR2)))) { + zqspi->inst_response = 0; + zynq_qspi_copy_read_data(zqspi, data, + zqspi->curr_inst->inst_size); + } else if (zqspi->bytes_to_receive < 4) { + zynq_qspi_copy_read_data(zqspi, data, + zqspi->bytes_to_receive); + } else { + zynq_qspi_copy_read_data(zqspi, data, + 4); + } + } + } + + if (zqspi->bytes_to_transfer) { + /* There is more data to send */ + zynq_qspi_fill_tx_fifo(zqspi); + + writel(ZYNQ_QSPI_IXR_ALL_MASK, &zynq_qspi_base->ier); + + config_reg = readl(&zynq_qspi_base->confr); + + config_reg |= ZYNQ_QSPI_CONFIG_MANSRT_MASK; + writel(config_reg, &zynq_qspi_base->confr); + } else { + /* + * If transfer and receive is completed then only send + * complete signal + */ + if (!zqspi->bytes_to_receive) { + /* return operation complete */ + writel(ZYNQ_QSPI_IXR_ALL_MASK, + &zynq_qspi_base->idisr); + return 1; + } + } + } + + return 0; +} + +/* + * zynq_qspi_start_transfer - Initiates the QSPI transfer + * @qspi: Pointer to the spi_device structure + * @transfer: Pointer to the spi_transfer structure which provide information + * about next transfer parameters + * + * This function fills the TX FIFO, starts the QSPI transfer, and waits for the + * transfer to be completed. + * + * returns: Number of bytes transferred in the last transfer + */ +static int zynq_qspi_start_transfer(struct spi_device *qspi, + struct spi_transfer *transfer) +{ + struct zynq_qspi *zqspi = &qspi->master; + static u8 current_u_page; + u32 config_reg; + u32 data = 0; + u8 instruction = 0; + u8 index; + + debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__, + (u32)qspi, (u32)transfer, transfer->len); + + zqspi->txbuf = transfer->tx_buf; + zqspi->rxbuf = transfer->rx_buf; + zqspi->bytes_to_transfer = transfer->len; + zqspi->bytes_to_receive = transfer->len; + + if (zqspi->txbuf) + instruction = *(u8 *)zqspi->txbuf; + + if (instruction && zqspi->is_inst) { + for (index = 0; index < ARRAY_SIZE(flash_inst); index++) + if (instruction == flash_inst[index].opcode) + break; + + /* + * Instruction might have already been transmitted. This is a + * 'data only' transfer + */ + if (index == ARRAY_SIZE(flash_inst)) + goto xfer_data; + + zqspi->curr_inst = &flash_inst[index]; + zqspi->inst_response = 1; + + if ((zqspi->is_dual == MODE_DUAL_STACKED) && + (current_u_page != zqspi->u_page)) { + if (zqspi->u_page) { + /* Configure two memories on shared bus + * by enabling upper mem + */ + writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | + ZYNQ_QSPI_LCFG_U_PAGE | + (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | + ZYNQ_QSPI_FR_QOUT_CODE), + &zynq_qspi_base->lcr); + } else { + /* Configure two memories on shared bus + * by enabling lower mem + */ + writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | + (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | + ZYNQ_QSPI_FR_QOUT_CODE), + &zynq_qspi_base->lcr); + } + + current_u_page = zqspi->u_page; + } + + /* Get the instruction */ + data = 0; + zynq_qspi_copy_write_data(zqspi, &data, + zqspi->curr_inst->inst_size); + + /* + * Write the instruction to LSB of the FIFO. The core is + * designed such that it is not necessary to check whether the + * write FIFO is full before writing. However, write would be + * delayed if the user tries to write when write FIFO is full + */ + writel(data, &zynq_qspi_base->confr + + (zqspi->curr_inst->offset / 4)); + + /* + * Read status register and Read ID instructions don't require + * to ignore the extra bytes in response of instruction as + * response contains the value + */ + if ((instruction == ZYNQ_QSPI_FLASH_OPCODE_RDSR1) || + (instruction == ZYNQ_QSPI_FLASH_OPCODE_RDSR2) || + (instruction == ZYNQ_QSPI_FLASH_OPCODE_RDID) || + (instruction == ZYNQ_QSPI_FLASH_OPCODE_BRRD) || + (instruction == ZYNQ_QSPI_FLASH_OPCODE_RDEAR)) { + if (zqspi->bytes_to_transfer < 4) + zqspi->bytes_to_transfer = 0; + else + zqspi->bytes_to_transfer -= 3; + } + } + +xfer_data: + /* + * In case of Fast, Dual and Quad reads, transmit the instruction first. + * Address and dummy byte should be transmitted after instruction + * is transmitted + */ + if (((zqspi->is_inst == 0) && (zqspi->bytes_to_transfer)) || + ((zqspi->bytes_to_transfer) && + (instruction != ZYNQ_QSPI_FLASH_OPCODE_FR) && + (instruction != ZYNQ_QSPI_FLASH_OPCODE_DR) && + (instruction != ZYNQ_QSPI_FLASH_OPCODE_QR) && + (instruction != ZYNQ_QSPI_FLASH_OPCODE_DIOR))) + zynq_qspi_fill_tx_fifo(zqspi); + + writel(ZYNQ_QSPI_IXR_ALL_MASK, &zynq_qspi_base->ier); + /* Start the transfer by enabling manual start bit */ + config_reg = readl(&zynq_qspi_base->confr) | + ZYNQ_QSPI_CONFIG_MANSRT_MASK; + writel(config_reg, &zynq_qspi_base->confr); + + /* wait for completion */ + do { + data = zynq_qspi_irq_poll(zqspi); + } while (data == 0); + + return (transfer->len) - (zqspi->bytes_to_transfer); +} + +static int zynq_qspi_transfer(struct spi_device *qspi, + struct spi_transfer *transfer) +{ + struct zynq_qspi *zqspi = &qspi->master; + unsigned cs_change = 1; + int status = 0; + + debug("%s\n", __func__); + + while (1) { + if (transfer->bits_per_word || transfer->speed_hz) { + status = zynq_qspi_setup_transfer(qspi, transfer); + if (status < 0) + break; + } + + /* Select the chip if required */ + if (cs_change) + zynq_qspi_chipselect(qspi, 1); + + cs_change = transfer->cs_change; + + if (!transfer->tx_buf && !transfer->rx_buf && transfer->len) { + status = -1; + break; + } + + /* Request the transfer */ + if (transfer->len) { + status = zynq_qspi_start_transfer(qspi, transfer); + zqspi->is_inst = 0; + } + + if (status != transfer->len) { + if (status > 0) + status = -EMSGSIZE; + break; + } + status = 0; + + if (transfer->delay_usecs) + udelay(transfer->delay_usecs); + + if (cs_change) + /* Deselect the chip */ + zynq_qspi_chipselect(qspi, 0); + + break; + } + + zynq_qspi_setup_transfer(qspi, NULL); + + return 0; +} + +/* + * zynq_qspi_check_is_dual_flash - checking for dual or single qspi + * + * This function will check the type of the flash whether it supports + * single or dual qspi based on the MIO configuration done by FSBL. + * + * User needs to correctly configure the MIO's based on the + * number of qspi flashes present on the board. + * + * function will return -1, if there is no MIO configuration for + * qspi flash. + */ +static int zynq_qspi_check_is_dual_flash(void) +{ + int is_dual = MODE_UNKNOWN; + int lower_mio = 0, upper_mio = 0, upper_mio_cs1 = 0; + + lower_mio = zynq_slcr_get_mio_pin_status("qspi0"); + if (lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) + is_dual = MODE_SINGLE; + + upper_mio_cs1 = zynq_slcr_get_mio_pin_status("qspi1_cs"); + if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) && + (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS)) + is_dual = MODE_DUAL_STACKED; + + upper_mio = zynq_slcr_get_mio_pin_status("qspi1"); + if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) && + (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS) && + (upper_mio == ZYNQ_QSPI_MIO_NUM_QSPI1)) + is_dual = MODE_DUAL_PARALLEL; + + return is_dual; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* 1 bus with 2 chipselect */ + return bus == 0 && cs < 2; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + debug("%s: slave 0x%08x\n", __func__, (unsigned)slave); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + debug("%s: slave 0x%08x\n", __func__, (unsigned)slave); +} + +void spi_init() +{ + debug("%s\n", __func__); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + int is_dual; + unsigned long lqspi_clk_ctrl_reg; + unsigned long lqspi_frequency; + struct zynq_qspi_slave *qspi; + + debug("%s: bus: %d cs: %d max_hz: %d mode: %d\n", + __func__, bus, cs, max_hz, mode); + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + is_dual = zynq_qspi_check_is_dual_flash(); + + if (is_dual == MODE_UNKNOWN) { + printf("%s: No QSPI device detected based on MIO settings\n", + __func__); + return NULL; + } + + zynq_qspi_init_hw(is_dual, cs); + + qspi = spi_alloc_slave(struct zynq_qspi_slave, bus, cs); + if (!qspi) { + printf("%s: Fail to allocate zynq_qspi_slave\n", __func__); + return NULL; + } + + /* + * Read the lqspi_clk_ctrl_reg register and calculate the frequency. + * If failure revert to 200Mhz + */ + lqspi_clk_ctrl_reg = zynq_slcr_get_lqspi_clk_ctrl(); + lqspi_frequency = (CONFIG_CPU_FREQ_HZ / ((lqspi_clk_ctrl_reg & 0x3F00)>> + 8)); + if (!lqspi_frequency) { + debug("Defaulting to 200000000 Hz qspi clk"); + qspi->qspi.master.input_clk_hz = 200000000; + } else { + qspi->qspi.master.input_clk_hz = lqspi_frequency; + debug("Qspi clk frequency set to %ld Hz\n", lqspi_frequency); + } + + qspi->slave.is_dual = is_dual; + qspi->slave.rd_cmd = READ_CMD_FULL; + qspi->slave.wr_cmd = PAGE_PROGRAM | QUAD_PAGE_PROGRAM; + qspi->qspi.master.speed_hz = qspi->qspi.master.input_clk_hz / 2; + qspi->qspi.max_speed_hz = qspi->qspi.master.speed_hz; + qspi->qspi.master.is_dual = is_dual; + qspi->qspi.mode = mode; + qspi->qspi.chip_select = 0; + qspi->qspi.bits_per_word = 32; + zynq_qspi_setup_transfer(&qspi->qspi, NULL); + + debug("%s: lqspi_clk_ctrl_reg: %ld CONFIG_CPU_FREQ_HZ %d\n", + __func__, lqspi_clk_ctrl_reg, CONFIG_CPU_FREQ_HZ); + + return &qspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct zynq_qspi_slave *qspi; + + debug("%s: slave: 0x%08x\n", __func__, (u32)slave); + + qspi = to_zynq_qspi_slave(slave); + free(qspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + debug("%s: slave: 0x%08x\n", __func__, (u32)slave); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + debug("%s: slave: 0x%08x\n", __func__, (u32)slave); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct zynq_qspi_slave *qspi; + struct spi_transfer transfer; + + debug("%s: slave: 0x%08x bitlen: %d dout: 0x%08x ", __func__, + (u32)slave, bitlen, (u32)dout); + debug("din: 0x%08x flags: 0x%lx\n", (u32)din, flags); + + qspi = (struct zynq_qspi_slave *)slave; + transfer.tx_buf = dout; + transfer.rx_buf = din; + transfer.len = bitlen / 8; + + /* + * Festering sore. + * Assume that the beginning of a transfer with bits to + * transmit must contain a device command. + */ + if (dout && flags & SPI_XFER_BEGIN) + qspi->qspi.master.is_inst = 1; + else + qspi->qspi.master.is_inst = 0; + + if (flags & SPI_XFER_END) + transfer.cs_change = 1; + else + transfer.cs_change = 0; + + if (flags & SPI_FLASH_U_PAGE) + qspi->qspi.master.u_page = 1; + else + qspi->qspi.master.u_page = 0; + + transfer.delay_usecs = 0; + transfer.bits_per_word = 32; + transfer.speed_hz = qspi->qspi.max_speed_hz; + + zynq_qspi_transfer(&qspi->qspi, &transfer); + + return 0; +} diff --cc include/configs/xilinx-ppc405-generic.h index 000afe59fed,75b119f8556..bb14c4cfcc9 --- a/include/configs/xilinx-ppc405-generic.h +++ b/include/configs/xilinx-ppc405-generic.h @@@ -1,29 -1,16 +1,13 @@@ /* + * (C) Copyright 2007-2010 Michal Simek * - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * - * (C) Copyright 2008 - * Georg Schardt + * Michal SIMEK * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_GEN_H -#define __CONFIG_GEN_H + +#ifndef __CONFIG_H +#define __CONFIG_H #include "../board/xilinx/ppc405-generic/xparameters.h" diff --cc include/configs/xilinx-ppc440-generic.h index 78c0dec7838,8e684151efe..a224241b55f --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@@ -1,26 -1,9 +1,10 @@@ /* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ + * (C) Copyright 2007-2010 Michal Simek + * + * Michal SIMEK + * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ -*/ + */ #ifndef __CONFIG_H #define __CONFIG_H diff --cc include/configs/zynq_afx.h index fe88cdf64dc,00000000000..b677585dab7 mode 100644,000000..100644 --- a/include/configs/zynq_afx.h +++ b/include/configs/zynq_afx.h @@@ -1,36 -1,0 +1,28 @@@ +/* + * (C) Copyright 2012 Xilinx + * + * Configuration settings for the Xilinx Zynq AFX board. + * See zynq_common.h for Zynq common configs + * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_AFX_H +#define __CONFIG_ZYNQ_AFX_H + +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 + +#define CONFIG_SYS_NO_FLASH +#if defined(CONFIG_AFX_NOR) +# undef CONFIG_SYS_NO_FLASH +#elif defined(CONFIG_AFX_QSPI) +# define CONFIG_ZYNQ_QSPI +#elif defined(CONFIG_AFX_NAND) +# define CONFIG_NAND_ZYNQ +#endif + +#include + +#endif /* __CONFIG_ZYNQ_AFX_H */ diff --cc include/configs/zynq_common.h index f8ff0acbb4a,00000000000..e20961be501 mode 100644,000000..100644 --- a/include/configs/zynq_common.h +++ b/include/configs/zynq_common.h @@@ -1,346 -1,0 +1,330 @@@ +/* + * (C) Copyright 2012 - 2013 Xilinx + * (C) Copyright 2012 Michal Simek + * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_H +#define __CONFIG_ZYNQ_H + +/* High Level Configuration Options */ +#define CONFIG_ARMV7 /* CPU */ +#define CONFIG_ZYNQ /* SoC */ + +/* Default environment */ +#define CONFIG_IPADDR 10.10.70.102 +#define CONFIG_SERVERIP 10.10.70.101 + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE + +/* TEXT BASE defines */ +#if defined(CONFIG_CSE_QSPI) || defined(CONFIG_CSE_NOR) +# define CONFIG_SYS_TEXT_BASE 0xFFFC4800 +#elif defined(CONFIG_CSE_NAND) +# define CONFIG_SYS_TEXT_BASE 0x00100000 +#else +# define CONFIG_SYS_TEXT_BASE 0x04000000 +#endif + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN 0x400000 + +/* Serial drivers */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } + +/* Zynq serial driver */ +#ifdef CONFIG_ZYNQ_SERIAL_UART0 +# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#endif + +#ifdef CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 +#endif + +#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) +#define CONFIG_ZYNQ_SERIAL +#endif + +/* DCC driver */ +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +# define CONFIG_SYS_ENET +#endif + +#ifndef CONFIG_CPU_FREQ_HZ +#define CONFIG_CPU_FREQ_HZ 800000000 +#endif +#define CONFIG_SYS_HZ 1000 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "zynq-uboot> " +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_LONGHELP +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +#include + +#ifdef CONFIG_SYS_ENET +# define CONFIG_CMD_PING +# define CONFIG_CMD_MII +#else +# undef CONFIG_CMD_NET +# undef CONFIG_CMD_NFS +#endif + +/* NOR */ +#ifndef CONFIG_SYS_NO_FLASH +# define CONFIG_SYS_FLASH_BASE 0xE2000000 +# define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors/blocks on one chip */ +# define CONFIG_SYS_MAX_FLASH_SECT 512 +# define CONFIG_SYS_FLASH_ERASE_TOUT 1000 +# define CONFIG_SYS_FLASH_WRITE_TOUT 5000 +# define CONFIG_FLASH_SHOW_PROGRESS 10 +# define CONFIG_SYS_FLASH_CFI +# undef CONFIG_SYS_FLASH_EMPTY_INFO +# define CONFIG_FLASH_CFI_DRIVER +# undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ +/* use buffered writes (20x faster) */ +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +# define CONFIG_ZYNQ_M29EW_WB_HACK +#endif + +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SPI +# define CONFIG_CMD_SF +#endif + +/* QSPI */ +#ifdef CONFIG_ZYNQ_QSPI +# define CONFIG_SF_DEFAULT_SPEED 30000000 +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_BAR +# define CONFIG_SPI_FLASH_SPANSION +# define CONFIG_SPI_FLASH_STMICRO +# define CONFIG_SPI_FLASH_WINBOND +# define CONFIG_CMD_SPI +# define CONFIG_CMD_SF +#endif + +/* MMC */ +#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_MMC +# define CONFIG_GENERIC_MMC +# define CONFIG_SDHCI +# define CONFIG_ZYNQ_SDHCI +# define CONFIG_CMD_MMC +# define CONFIG_CMD_FAT +# define CONFIG_SUPPORT_VFAT +# define CONFIG_CMD_EXT2 +# define CONFIG_DOS_PARTITION +#endif + +/* NAND */ +#ifdef CONFIG_NAND_ZYNQ +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_SELF_INIT +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_MTD_DEVICE +#endif + +/* I2C */ +#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) +# define CONFIG_CMD_I2C +# define CONFIG_ZYNQ_I2C - # define CONFIG_HARD_I2C ++/* # define CONFIG_SYS_I2C */ +# define CONFIG_SYS_I2C_SPEED 100000 +# define CONFIG_SYS_I2C_SLAVE 1 +#endif + +/* EEPROM */ +#ifdef CONFIG_ZYNQ_EEPROM +# define CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ +#endif + +#ifndef CONFIG_ENV_IS_NOWHERE +# ifndef CONFIG_SYS_NO_FLASH +/* Environment in NOR flash */ +# define CONFIG_ENV_IS_IN_FLASH +# elif defined(CONFIG_ZYNQ_QSPI) +/* Environment in Serial Flash */ +# define CONFIG_ENV_IS_IN_SPI_FLASH +# elif defined(CONFIG_NAND_ZYNQ) +/* Environment in NAND flash */ +# define CONFIG_ENV_IS_IN_NAND +# elif defined(CONFIG_SYS_NO_FLASH) +# define CONFIG_ENV_IS_NOWHERE +# endif + +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +# define CONFIG_ENV_OFFSET 0xE0000 +# define CONFIG_CMD_SAVEENV /* Command to save ENV to Flash */ +#endif + +/* For development/debugging */ +#ifdef DEBUG +# define CONFIG_CMD_REGINFO +# define CONFIG_PANIC_HANG +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ethaddr=00:0a:35:00:01:22\0" \ + "kernel_image=uImage\0" \ + "ramdisk_image=uramdisk.image.gz\0" \ + "devicetree_image=devicetree.dtb\0" \ + "bitstream_image=system.bit.bin\0" \ + "loadbit_addr=0x100000\0" \ + "loadbootenv_addr=0x2000000\0" \ + "kernel_size=0x500000\0" \ + "devicetree_size=0x20000\0" \ + "ramdisk_size=0x5E0000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc 0 ${loadbootenv_addr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from SD ...; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \ + "mmcinfo && " \ + "fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \ + "fpga load 0 ${loadbit_addr} ${filesize}\0" \ + "norboot=echo Copying Linux from NOR flash to RAM... && " \ + "cp.b 0xE2100000 0x3000000 ${kernel_size} && " \ + "cp.b 0xE2600000 0x2A00000 ${devicetree_size} && " \ + "echo Copying ramdisk... && " \ + "cp.b 0xE2620000 0x2000000 ${ramdisk_size} && " \ + "bootm 0x3000000 0x2000000 0x2A00000\0" \ + "qspiboot=echo Copying Linux from QSPI flash to RAM... && " \ + "sf probe 0 0 0 && " \ + "sf read 0x3000000 0x100000 ${kernel_size} && " \ + "sf read 0x2A00000 0x600000 ${devicetree_size} && " \ + "echo Copying ramdisk... && " \ + "sf read 0x2000000 0x620000 ${ramdisk_size} && " \ + "bootm 0x3000000 0x2000000 0x2A00000\0" \ + "uenvboot=" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv}; " \ + "run importbootenv; " \ + "fi; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi\0" \ + "sdboot=if mmcinfo; then " \ + "run uenvboot; " \ + "echo Copying Linux from SD to RAM... && " \ + "fatload mmc 0 0x3000000 ${kernel_image} && " \ + "fatload mmc 0 0x2A00000 ${devicetree_image} && " \ + "fatload mmc 0 0x2000000 ${ramdisk_image} && " \ + "bootm 0x3000000 0x2000000 0x2A00000; " \ + "fi\0" \ + "nandboot=echo Copying Linux from NAND flash to RAM... && " \ + "nand read 0x3000000 0x100000 ${kernel_size} && " \ + "nand read 0x2A00000 0x600000 ${devicetree_size} && " \ + "echo Copying ramdisk... && " \ + "nand read 0x2000000 0x620000 ${ramdisk_size} && " \ + "bootm 0x3000000 0x2000000 0x2A00000\0" \ + "jtagboot=echo TFTPing Linux to RAM... && " \ + "tftp 0x3000000 ${kernel_image} && " \ + "tftp 0x2A00000 ${devicetree_image} && " \ + "tftp 0x2000000 ${ramdisk_image} && " \ + "bootm 0x3000000 0x2000000 0x2A00000\0" + +/* default boot is according to the bootmode switch settings */ +#define CONFIG_BOOTCOMMAND "run $modeboot" +#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ + +#define CONFIG_CMD_CACHE + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + +/* Physical Memory map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + PHYS_SDRAM_1_SIZE - (16 * 1024 * 1024)) + +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Enable the PL to be downloaded */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA + +/* FIT support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* Boot FreeBSD/vxWorks from an ELF image */ +#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) +# define CONFIG_API +# define CONFIG_CMD_ELF +# define CONFIG_SYS_MMC_MAX_DEVICE 1 +#endif + +#define CONFIG_CMD_BOOTZ +#undef CONFIG_BOOTM_NETBSD + +#endif /* __CONFIG_ZYNQ_H */ diff --cc include/configs/zynq_zc70x.h index c98e7025201,00000000000..206ffd35518 mode 100644,000000..100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@@ -1,37 -1,0 +1,29 @@@ +/* + * (C) Copyright 2012 Xilinx + * + * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards + * See zynq_common.h for Zynq common configs + * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZC70X_H +#define __CONFIG_ZYNQ_ZC70X_H + +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_QSPI +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_EEPROM +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include + +#endif /* __CONFIG_ZYNQ_ZC70X_H */ diff --cc include/configs/zynq_zc770.h index 190781f02a4,00000000000..1df5b7a7877 mode 100644,000000..100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@@ -1,52 -1,0 +1,44 @@@ +/* + * (C) Copyright 2012 Xilinx + * + * Configuration settings for the Xilinx Zynq ZC770 board. + * See zynq_common.h for Zynq common configs + * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZC770_H +#define __CONFIG_ZYNQ_ZC770_H + +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_NO_FLASH + +#if defined(CONFIG_ZC770_XM010) +# define CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_ZYNQ_GEM0 +# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 +# define CONFIG_ZYNQ_SDHCI0 +# define CONFIG_ZYNQ_QSPI + +#elif defined(CONFIG_ZC770_XM011) +# define CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_NAND_ZYNQ + +#elif defined(CONFIG_ZC770_XM012) +# define CONFIG_ZYNQ_SERIAL_UART1 +# undef CONFIG_SYS_NO_FLASH + +#elif defined(CONFIG_ZC770_XM013) +# define CONFIG_ZYNQ_SERIAL_UART0 +# define CONFIG_ZYNQ_GEM1 +# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7 +# define CONFIG_ZYNQ_QSPI + +#else +# define CONFIG_ZYNQ_SERIAL_UART0 +#endif + +#include + +#endif /* __CONFIG_ZYNQ_ZC770_H */ diff --cc include/configs/zynq_zed.h index e4ba3f08459,00000000000..71a1beffb95 mode 100644,000000..100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@@ -1,35 -1,0 +1,27 @@@ +/* + * (C) Copyright 2012 Xilinx + * + * Configuration for Zynq Evaluation and Development Board - ZedBoard + * See zynq_common.h for Zynq common configs + * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZED_H +#define __CONFIG_ZYNQ_ZED_H + +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_QSPI +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include + +#endif /* __CONFIG_ZYNQ_ZED_H */ diff --cc include/spi.h index d65d3924d23,ad9248bee02..b0ddd435f7c --- a/include/spi.h +++ b/include/spi.h @@@ -41,9 -25,10 +25,11 @@@ #define SPI_PREAMBLE 0x80 /* Skip preamble bytes */ /* SPI transfer flags */ - #define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ - #define SPI_XFER_END 0x02 /* Deassert CS after transfer */ - #define SPI_FLASH_U_PAGE 0x04 /* Enable Upper memory page */ + #define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ + #define SPI_XFER_END 0x02 /* Deassert CS after transfer */ ++#define SPI_FLASH_U_PAGE 0x04 /* Enable Upper memory page */ + #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ + #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec @@@ -53,26 -38,20 +39,28 @@@ * * Drivers are expected to extend this with controller-specific data. * - * bus: ID of the bus that the slave is attached to. - * cs: ID of the chip select connected to the slave. + * @bus: ID of the bus that the slave is attached to. + * @cs: ID of the chip select connected to the slave. + * is_dual: Indicates whether dual memories are used + * u_page: Indicates the upper memory page, in dual stacked connection. - * max_write_size: If non-zero, the maximum number of bytes which can - * be written at once, excluding command bytes. + * @max_write_size: If non-zero, the maximum number of bytes which can + * be written at once, excluding command bytes. + * @memory_map: Address of read-only SPI flash access. + * rd_cmd: Read command. + * wr_cmd: Write command. */ struct spi_slave { - unsigned int bus; - unsigned int cs; + unsigned int bus; + unsigned int cs; + unsigned int is_dual; + unsigned int u_page; unsigned int max_write_size; + void *memory_map; + u8 rd_cmd; + u8 wr_cmd; }; - /*----------------------------------------------------------------------- + /** * Initialization, must be called once on start up. * * TODO: I don't think we really need this. diff --cc include/spi_flash.h index a6091f8063e,25ca8f177b3..b744e5a0ca1 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@@ -27,107 -19,52 +19,85 @@@ #include #include +/* SPI connection modes */ +enum spi_con_topology { + MODE_UNKNOWN = -1, + MODE_SINGLE, + MODE_DUAL_STACKED, + MODE_DUAL_PARALLEL, +}; + +/* Default read and write commands */ +#define CMD_PAGE_PROGRAM 0x02 +#define CMD_READ_ARRAY_FAST 0x0b + +enum spi_write_cmds { + PAGE_PROGRAM = 1 << 0, + QUAD_PAGE_PROGRAM = 1 << 1, +}; + +enum spi_read_cmds { + ARRAY_SLOW = 1 << 0, + ARRAY_FAST = 1 << 1, + DUAL_OUTPUT_FAST = 1 << 2, + DUAL_IO_FAST = 1 << 3, + QUAD_OUTPUT_FAST = 1 << 4, +}; + +#define READ_CMD_FULL ARRAY_SLOW | ARRAY_FAST | DUAL_OUTPUT_FAST | \ + DUAL_IO_FAST | QUAD_OUTPUT_FAST + + /** + * struct spi_flash - SPI flash structure + * + * @spi: SPI slave + * @name: Name of SPI flash + * @size: Total flash size + * @page_size: Write (page) size + * @sector_size: Sector size + * @erase_size: Erase size + * @bank_read_cmd: Bank read cmd + * @bank_write_cmd: Bank write cmd + * @bank_curr: Current flash bank + * @poll_cmd: Poll cmd - for flash erase/program + * @erase_cmd: Erase cmd 4K, 32K, 64K + * @memory_map: Address of read-only SPI flash access + * @read: Flash read ops: Read len bytes at offset into buf + * Supported cmds: Fast Array Read + * @write: Flash write ops: Write len bytes from buf into offeset + * Supported cmds: Page Program + * @erase: Flash erase ops: Erase len bytes from offset + * Supported cmds: Sector erase 4K, 32K, 64K + * return 0 - Sucess, 1 - Failure + */ struct spi_flash { struct spi_slave *spi; + const char *name; - const char *name; - - /* Total flash size */ - u32 size; - /* Write (page) size */ - u32 page_size; - /* Erase (sector) size */ - u32 sector_size; + u32 size; + u32 page_size; + u32 sector_size; + u32 erase_size; #ifdef CONFIG_SPI_FLASH_BAR - /* Bank read cmd */ - u8 bank_read_cmd; - /* Bank write cmd */ - u8 bank_write_cmd; - /* Current flash bank */ - u8 bank_curr; + u8 bank_read_cmd; + u8 bank_write_cmd; + u8 bank_curr; #endif - u8 poll_cmd; + /* Poll cmd - for flash erase/program */ + u8 poll_cmd; + /* Read command */ + u8 read_cmd; + /* Write command */ + u8 write_cmd; + u8 erase_cmd; - void *memory_map; /* Address of read-only SPI flash access */ - int (*read)(struct spi_flash *flash, u32 offset, - size_t len, void *buf); - int (*write)(struct spi_flash *flash, u32 offset, - size_t len, const void *buf); - int (*erase)(struct spi_flash *flash, u32 offset, - size_t len); + void *memory_map; + int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); + int (*write)(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); + int (*erase)(struct spi_flash *flash, u32 offset, size_t len); }; - /** - * spi_flash_do_alloc - Allocate a new spi flash structure - * - * The structure is allocated and cleared with default values for - * read, write and erase, which the caller can modify. The caller must set - * up size, page_size and sector_size. - * - * Use the helper macro spi_flash_alloc() to call this. - * - * @offset: Offset of struct spi_slave within slave structure - * @size: Size of slave structure - * @spi: SPI slave - * @name: Name of SPI flash device - */ - void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, - const char *name); - - /** - * spi_flash_alloc - Allocate a new SPI flash structure - * - * @_struct: Name of structure to allocate (e.g. struct ramtron_spi_fram). This - * structure must contain a member 'struct spi_flash *flash'. - * @spi: SPI slave - * @name: Name of SPI flash device - */ - #define spi_flash_alloc(_struct, spi, name) \ - spi_flash_do_alloc(offsetof(_struct, flash), sizeof(_struct), \ - spi, name) - - /** - * spi_flash_alloc_base - Allocate a new SPI flash structure with no private data - * - * @spi: SPI slave - * @name: Name of SPI flash device - */ - #define spi_flash_alloc_base(spi, name) \ - spi_flash_do_alloc(0, sizeof(struct spi_flash), spi, name) - struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode); void spi_flash_free(struct spi_flash *flash);