From: Vidya Sagar Date: Tue, 24 Mar 2026 19:09:56 +0000 (+0530) Subject: PCI: tegra194: Enable hardware hot reset mode in Endpoint mode X-Git-Tag: v7.1-rc1~151^2~4^2~2 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=acd46d51f22f0d4b83d4e34088e68498110085b5;p=thirdparty%2Fkernel%2Flinux.git PCI: tegra194: Enable hardware hot reset mode in Endpoint mode When PCIe link goes down, hardware can retrain the link and try to link up. To enable this feature, program the APPL_CTRL register with hardware hot reset with immediate LTSSM enable mode when the controller is operating in endpoint mode. Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy [mani: commit log] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Tested-by: Jon Hunter Reviewed-by: Jon Hunter Reviewed-by: Vidya Sagar Link: https://patch.msgid.link/20260324191000.1095768-6-mmaddireddy@nvidia.com --- diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 409f8eaceb395..eeb93cc1200a3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1796,6 +1796,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val = appl_readl(pcie, APPL_CTRL); val |= APPL_CTRL_SYS_PRE_DET_STATE; val |= APPL_CTRL_HW_HOT_RST_EN; + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT); + val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT); appl_writel(pcie, val, APPL_CTRL); val = appl_readl(pcie, APPL_CFG_MISC);