From: George Moussalem Date: Wed, 15 Jul 2026 09:09:55 +0000 (+0400) Subject: qualcommax: ipq50xx: backport upstreamed patches for IPQ5018 PHY clocks X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=ad1de384bf93d44503a13cb3983f35001dd511ef;p=thirdparty%2Fopenwrt.git qualcommax: ipq50xx: backport upstreamed patches for IPQ5018 PHY clocks Backport upstreamed patches for IPQ5018 PHY RX and TX clocks support. Signed-off-by: George Moussalem Link: https://github.com/openwrt/openwrt/pull/24238 Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommax/patches-6.12/0086-v6.17-dt-bindings-net-qca-ar803x-Add-IPQ5018-Internal-GE-PHY-support.patch b/target/linux/qualcommax/patches-6.12/0086-v6.17-dt-bindings-net-qca-ar803x-Add-IPQ5018-Internal-GE-PHY-support.patch new file mode 100644 index 00000000000..52ff962cf4d --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0086-v6.17-dt-bindings-net-qca-ar803x-Add-IPQ5018-Internal-GE-PHY-support.patch @@ -0,0 +1,90 @@ +From 82eaf94d69fce20f8859a2b8dae8e7064d9343da Mon Sep 17 00:00:00 2001 +From: George Moussalem +Date: Fri, 13 Jun 2025 05:55:07 +0400 +Subject: [PATCH] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY + support + +Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018 +SoC. Its output pins provide an MDI interface to either an external +switch in a PHY to PHY link scenario or is directly attached to an RJ45 +connector. + +The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and +802.3az EEE. + +For operation, the LDO controller found in the IPQ5018 SoC for which +there is provision in the mdio-4019 driver. + +Two common archictures across IPQ5018 boards are: +1. IPQ5018 PHY --> MDI --> RJ45 connector +2. IPQ5018 PHY --> MDI --> External PHY +In a phy to phy architecture, the DAC needs to be configured to +accommodate for the short cable length. As such, add an optional boolean +property so the driver sets preset DAC register values accordingly. + +Signed-off-by: George Moussalem +Reviewed-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20250613-ipq5018-ge-phy-v5-1-9af06e34ea6b@outlook.com +Signed-off-by: Jakub Kicinski +--- + .../devicetree/bindings/net/qca,ar803x.yaml | 43 +++++++++++++++++++ + 1 file changed, 43 insertions(+) + +--- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml ++++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml +@@ -16,8 +16,37 @@ description: | + + allOf: + - $ref: ethernet-phy.yaml# ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - ethernet-phy-id004d.d0c0 ++ ++ then: ++ properties: ++ reg: ++ const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC ++ ++ resets: ++ items: ++ - description: ++ GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines. ++ ++ qcom,dac-preset-short-cable: ++ description: ++ Set if this phy is connected to another phy to adjust the values for ++ MDAC and EDAC to adjust amplitude, bias current settings, and error ++ detection and correction algorithm to accommodate for short cable length. ++ If not set, DAC values are not modified and it is assumed the MDI output pins ++ of this PHY are directly connected to an RJ45 connector. ++ type: boolean + + properties: ++ compatible: ++ enum: ++ - ethernet-phy-id004d.d0c0 ++ + qca,clk-out-frequency: + description: Clock output frequency in Hertz. + $ref: /schemas/types.yaml#/definitions/uint32 +@@ -132,3 +161,17 @@ examples: + }; + }; + }; ++ - | ++ #include ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ge_phy: ethernet-phy@7 { ++ compatible = "ethernet-phy-id004d.d0c0"; ++ reg = <7>; ++ ++ resets = <&gcc GCC_GEPHY_MISC_ARES>; ++ }; ++ }; diff --git a/target/linux/qualcommax/patches-6.12/0740-01-dt-bindings-net-ethernet-phy-increase-max-clock-count-to-two.patch b/target/linux/qualcommax/patches-6.12/0087-v7.2-dt-bindings-net-ethernet-phy-increase-max-clock-count-to-two.patch similarity index 64% rename from target/linux/qualcommax/patches-6.12/0740-01-dt-bindings-net-ethernet-phy-increase-max-clock-count-to-two.patch rename to target/linux/qualcommax/patches-6.12/0087-v7.2-dt-bindings-net-ethernet-phy-increase-max-clock-count-to-two.patch index 57285d0595f..73d6975eca1 100644 --- a/target/linux/qualcommax/patches-6.12/0740-01-dt-bindings-net-ethernet-phy-increase-max-clock-count-to-two.patch +++ b/target/linux/qualcommax/patches-6.12/0087-v7.2-dt-bindings-net-ethernet-phy-increase-max-clock-count-to-two.patch @@ -1,11 +1,8 @@ -From 009bdd7a91990982e5b3bab4001318dfe5f6f575 Mon Sep 17 00:00:00 2001 +From 19e00bdfbb1b5f7a2d1f3c1c38b3da25e17ea486 Mon Sep 17 00:00:00 2001 From: George Moussalem -Date: Sun, 07 Jun 2026 13:00:06 +0400 -Subject: [PATCH v4 1/4] dt-bindings: net: ethernet-phy: increase max clock count to two -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit -Message-Id: <20260607-ipq5018-gephy-clocks-v4-1-15b3a5ba7460@outlook.com> +Date: Mon, 8 Jun 2026 09:09:16 +0400 +Subject: [PATCH] dt-bindings: net: ethernet-phy: increase max clock count to + two The clocks property has a restriction to maximum one. Yet, some PHYs may require more than 1 clock such as the IPQ5018 PHY @@ -14,12 +11,8 @@ two. Reviewed-by: Rob Herring (Arm) Signed-off-by: George Moussalem ---- -Commit 350b7a258f20 introduced the clocks property with a restriction to -maximum 1 to the main ethernet-phy.yaml binding for Realtek to add an -optional external clock source. This is restrictive to all PHY bindings, -as some PHYs may require more than 1 clock such as the IPQ5018 PHY which -requires 2 clocks (for RX and TX). +Link: https://patch.msgid.link/20260608-ipq5018-gephy-clocks-v4-1-fb2ccd56894b@outlook.com +Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/linux/qualcommax/patches-6.12/0088-v7.2-dt-bindings-net-qca-ar803x-Add-clocks-for-IPQ5018-PHY.patch b/target/linux/qualcommax/patches-6.12/0088-v7.2-dt-bindings-net-qca-ar803x-Add-clocks-for-IPQ5018-PHY.patch new file mode 100644 index 00000000000..d410a241871 --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0088-v7.2-dt-bindings-net-qca-ar803x-Add-clocks-for-IPQ5018-PHY.patch @@ -0,0 +1,66 @@ +From fea4ae4b5b5059612d1a4f5acb88c27a5f7e60dc Mon Sep 17 00:00:00 2001 +From: George Moussalem +Date: Mon, 8 Jun 2026 09:09:17 +0400 +Subject: [PATCH] dt-bindings: net: qca,ar803x: Add clocks for IPQ5018 PHY + +Further testing revealed that the RX and TX clocks of the IPQ5018 PHY +need to be explicitly enabled. As such, add the required clocks to the +schema. + +Acked-by: Conor Dooley +Signed-off-by: George Moussalem +Link: https://patch.msgid.link/20260608-ipq5018-gephy-clocks-v4-2-fb2ccd56894b@outlook.com +Signed-off-by: Jakub Kicinski +--- + .../devicetree/bindings/net/qca,ar803x.yaml | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml ++++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml +@@ -28,6 +28,16 @@ allOf: + reg: + const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC + ++ clocks: ++ items: ++ - description: RX clock ++ - description: TX clock ++ ++ clock-names: ++ items: ++ - const: rx ++ - const: tx ++ + resets: + items: + - description: +@@ -42,6 +52,11 @@ allOf: + of this PHY are directly connected to an RJ45 connector. + type: boolean + ++ required: ++ - clocks ++ - clock-names ++ - resets ++ + properties: + compatible: + enum: +@@ -162,6 +177,7 @@ examples: + }; + }; + - | ++ #include + #include + + mdio { +@@ -172,6 +188,9 @@ examples: + compatible = "ethernet-phy-id004d.d0c0"; + reg = <7>; + ++ clocks = <&gcc GCC_GEPHY_RX_CLK>, ++ <&gcc GCC_GEPHY_TX_CLK>; ++ clock-names = "rx", "tx"; + resets = <&gcc GCC_GEPHY_MISC_ARES>; + }; + }; diff --git a/target/linux/qualcommax/patches-6.12/0089-v7.2-net-phy-at803x-add-RX-and-TX-clock-management-for-IPQ5018-PHY.patch b/target/linux/qualcommax/patches-6.12/0089-v7.2-net-phy-at803x-add-RX-and-TX-clock-management-for-IPQ5018-PHY.patch new file mode 100644 index 00000000000..4a43b525494 --- /dev/null +++ b/target/linux/qualcommax/patches-6.12/0089-v7.2-net-phy-at803x-add-RX-and-TX-clock-management-for-IPQ5018-PHY.patch @@ -0,0 +1,51 @@ +From cf6077e4903ffed2291f5f3cb9d61b29abe456c4 Mon Sep 17 00:00:00 2001 +From: George Moussalem +Date: Mon, 8 Jun 2026 09:09:19 +0400 +Subject: [PATCH] net: phy: at803x: add RX and TX clock management for IPQ5018 + PHY + +Acquire and enable the RX and TX clocks for the IPQ5018 PHY. +These clocks are required for the PHY's datapath to function correctly. + +Signed-off-by: George Moussalem +Link: https://patch.msgid.link/20260608-ipq5018-gephy-clocks-v4-4-fb2ccd56894b@outlook.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/qcom/at803x.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1089,6 +1090,7 @@ static void ipq5018_link_change_notify(s + static int ipq5018_probe(struct phy_device *phydev) + { + struct device *dev = &phydev->mdio.dev; ++ struct clk *rx_clk, *tx_clk; + struct ipq5018_priv *priv; + int ret; + +@@ -1099,6 +1101,16 @@ static int ipq5018_probe(struct phy_devi + priv->set_short_cable_dac = of_property_read_bool(dev->of_node, + "qcom,dac-preset-short-cable"); + ++ rx_clk = devm_clk_get_enabled(dev, "rx"); ++ if (IS_ERR(rx_clk)) ++ return dev_err_probe(dev, PTR_ERR(rx_clk), ++ "failed to get and enable RX clock\n"); ++ ++ tx_clk = devm_clk_get_enabled(dev, "tx"); ++ if (IS_ERR(tx_clk)) ++ return dev_err_probe(dev, PTR_ERR(tx_clk), ++ "failed to get and enable TX clock\n"); ++ + priv->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), diff --git a/target/linux/qualcommax/patches-6.12/0740-03-arm64-qcom-ipq5018-add-gephy-rx-and-tx-clocks.patch b/target/linux/qualcommax/patches-6.12/0090-v7.3-arm64-qcom-ipq5018-Add-GEPHY-RX-and-TX-clocks.patch similarity index 66% rename from target/linux/qualcommax/patches-6.12/0740-03-arm64-qcom-ipq5018-add-gephy-rx-and-tx-clocks.patch rename to target/linux/qualcommax/patches-6.12/0090-v7.3-arm64-qcom-ipq5018-Add-GEPHY-RX-and-TX-clocks.patch index 0e2aed96976..b77a83403cd 100644 --- a/target/linux/qualcommax/patches-6.12/0740-03-arm64-qcom-ipq5018-add-gephy-rx-and-tx-clocks.patch +++ b/target/linux/qualcommax/patches-6.12/0090-v7.3-arm64-qcom-ipq5018-Add-GEPHY-RX-and-TX-clocks.patch @@ -1,24 +1,24 @@ -From ea59840c0b6839c65eaf39887a0762dfc4993f50 Mon Sep 17 00:00:00 2001 +From 20959cefc27e7e2e506b4e789b728e5702c77f95 Mon Sep 17 00:00:00 2001 From: George Moussalem -Date: Sun, 07 Jun 2026 13:00:08 +0400 -Subject: [PATCH v4 3/4] arm64: qcom: ipq5018: Add GEPHY RX and TX clocks -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit -Message-Id: <20260607-ipq5018-gephy-clocks-v4-3-15b3a5ba7460@outlook.com> +Date: Mon, 8 Jun 2026 09:09:18 +0400 +Subject: arm64: qcom: ipq5018: Add GEPHY RX and TX clocks Add RX and TX clocks for the IPQ5018 GEPHY to enable the datapath. Fixes: f5f2b835e316 ("arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus") Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem +Link: https://lore.kernel.org/r/20260608-ipq5018-gephy-clocks-v4-3-fb2ccd56894b@outlook.com +Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 +++ 1 file changed, 3 insertions(+) +(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') + --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -234,6 +234,9 @@ +@@ -229,6 +229,9 @@ compatible = "ethernet-phy-id004d.d0c0"; reg = <7>; diff --git a/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch b/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch index 7620bb53e1b..ee1c5738fd6 100644 --- a/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch +++ b/target/linux/qualcommax/patches-6.12/0189-arm64-dts-qcom-ipq5018-add-nodes-to-bringup-q6.patch @@ -28,7 +28,7 @@ Signed-off-by: George Moussalem }; soc: soc@0 { -@@ -731,6 +736,41 @@ +@@ -734,6 +739,41 @@ }; }; @@ -70,7 +70,7 @@ Signed-off-by: George Moussalem pcie1: pcie@80000000 { compatible = "qcom,pcie-ipq5018"; reg = <0x80000000 0xf1d>, -@@ -1005,4 +1045,28 @@ +@@ -1008,4 +1048,28 @@ , ; }; diff --git a/target/linux/qualcommax/patches-6.12/0740-04-net-phy-at803x-add-rx-and-tx-clock-management-for-ipq5018-phy.patch b/target/linux/qualcommax/patches-6.12/0740-04-net-phy-at803x-add-rx-and-tx-clock-management-for-ipq5018-phy.patch deleted file mode 100644 index de781809f56..00000000000 --- a/target/linux/qualcommax/patches-6.12/0740-04-net-phy-at803x-add-rx-and-tx-clock-management-for-ipq5018-phy.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 929c734775fc0e4f576727b47f8a07d7e5cabb4f Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Sun, 07 Jun 2026 13:00:09 +0400 -Subject: [PATCH v4 4/4] net: phy: at803x: add RX and TX clock management for IPQ5018 PHY -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit -Message-Id: <20260607-ipq5018-gephy-clocks-v4-4-15b3a5ba7460@outlook.com> - -Acquire and enable the RX and TX clocks for the IPQ5018 PHY. -These clocks are required for the PHY's datapath to function correctly. - -Fixes: d46502279a11 ("net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support") -Signed-off-by: George Moussalem ---- - drivers/net/phy/qcom/at803x.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/net/phy/qcom/at803x.c -+++ b/drivers/net/phy/qcom/at803x.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -176,6 +177,8 @@ struct at803x_context { - }; - - struct ipq5018_priv { -+ struct clk *rx_clk; -+ struct clk *tx_clk; - struct reset_control *rst; - bool set_short_cable_dac; - }; -@@ -1099,6 +1102,16 @@ static int ipq5018_probe(struct phy_devi - priv->set_short_cable_dac = of_property_read_bool(dev->of_node, - "qcom,dac-preset-short-cable"); - -+ priv->rx_clk = devm_clk_get_enabled(dev, "rx"); -+ if (IS_ERR(priv->rx_clk)) -+ return dev_err_probe(dev, PTR_ERR(priv->rx_clk), -+ "failed to get and enable RX clock\n"); -+ -+ priv->tx_clk = devm_clk_get_enabled(dev, "tx"); -+ if (IS_ERR(priv->tx_clk)) -+ return dev_err_probe(dev, PTR_ERR(priv->tx_clk), -+ "failed to get and enable TX clock\n"); -+ - priv->rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(priv->rst)) - return dev_err_probe(dev, PTR_ERR(priv->rst),