From: Greg Kroah-Hartman Date: Thu, 7 Sep 2023 10:21:07 +0000 (+0100) Subject: 6.5-stable patches X-Git-Tag: v6.1.53~148 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=aeb0e0698c2098dee9d29f50b830db7adac6e1cd;p=thirdparty%2Fkernel%2Fstable-queue.git 6.5-stable patches added patches: cpufreq-intel_pstate-set-stale-cpu-frequency-to-minimum.patch drm-amd-display-ensure-async-flips-are-only-accepted-for-fast-updates.patch series tpm-enable-hwrng-only-for-pluton-on-amd-cpus.patch --- diff --git a/queue-6.5/cpufreq-intel_pstate-set-stale-cpu-frequency-to-minimum.patch b/queue-6.5/cpufreq-intel_pstate-set-stale-cpu-frequency-to-minimum.patch new file mode 100644 index 00000000000..e4a9301415b --- /dev/null +++ b/queue-6.5/cpufreq-intel_pstate-set-stale-cpu-frequency-to-minimum.patch @@ -0,0 +1,47 @@ +From d51847acb018d83186e4af67bc93f9a00a8644f7 Mon Sep 17 00:00:00 2001 +From: Doug Smythies +Date: Sun, 20 Aug 2023 13:46:49 -0700 +Subject: cpufreq: intel_pstate: set stale CPU frequency to minimum + +From: Doug Smythies + +commit d51847acb018d83186e4af67bc93f9a00a8644f7 upstream. + +The intel_pstate CPU frequency scaling driver does not +use policy->cur and it is 0. +When the CPU frequency is outdated arch_freq_get_on_cpu() +will default to the nominal clock frequency when its call to +cpufreq_quick_getpolicy_cur returns the never updated 0. +Thus, the listed frequency might be outside of currently +set limits. Some users are complaining about the high +reported frequency, albeit stale, when their system is +idle and/or it is above the reduced maximum they have set. + +This patch will maintain policy_cur for the intel_pstate +driver at the current minimum CPU frequency. + +Reported-by: Yang Jie +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217597 +Signed-off-by: Doug Smythies +[ rjw: White space damage fixes and comment adjustment ] +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Keyon Jie +Signed-off-by: Greg Kroah-Hartman +--- + drivers/cpufreq/intel_pstate.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/cpufreq/intel_pstate.c ++++ b/drivers/cpufreq/intel_pstate.c +@@ -2609,6 +2609,11 @@ static int intel_pstate_set_policy(struc + intel_pstate_clear_update_util_hook(policy->cpu); + intel_pstate_hwp_set(policy->cpu); + } ++ /* ++ * policy->cur is never updated with the intel_pstate driver, but it ++ * is used as a stale frequency value. So, keep it within limits. ++ */ ++ policy->cur = policy->min; + + mutex_unlock(&intel_pstate_limits_lock); + diff --git a/queue-6.5/drm-amd-display-ensure-async-flips-are-only-accepted-for-fast-updates.patch b/queue-6.5/drm-amd-display-ensure-async-flips-are-only-accepted-for-fast-updates.patch new file mode 100644 index 00000000000..f87fe5893b5 --- /dev/null +++ b/queue-6.5/drm-amd-display-ensure-async-flips-are-only-accepted-for-fast-updates.patch @@ -0,0 +1,101 @@ +From a7c0cad0dc060bb77e9c9d235d68441b0fc69507 Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Fri, 4 Aug 2023 11:13:04 -0400 +Subject: drm/amd/display: ensure async flips are only accepted for fast updates + +From: Hamza Mahfooz + +commit a7c0cad0dc060bb77e9c9d235d68441b0fc69507 upstream. + +We should be checking to see if async flips are supported in +amdgpu_dm_atomic_check() (i.e. not dm_crtc_helper_atomic_check()). Also, +async flipping isn't supported if a plane's framebuffer changes memory +domains during an atomic commit. So, move the check from +dm_crtc_helper_atomic_check() to amdgpu_dm_atomic_check() and check if +the memory domain has changed in amdgpu_dm_atomic_check(). + +Cc: stable@vger.kernel.org +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2733 +Fixes: c1e18c44dc7f ("drm/amd/display: only accept async flips for fast updates") +Reviewed-by: Harry Wentland +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Reported-by: Michael Larabel +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 ++++++++++++++--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 12 -------- + 2 files changed, 21 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -8074,10 +8074,12 @@ static void amdgpu_dm_commit_planes(stru + * fast updates. + */ + if (crtc->state->async_flip && +- acrtc_state->update_type != UPDATE_TYPE_FAST) ++ (acrtc_state->update_type != UPDATE_TYPE_FAST || ++ get_mem_type(old_plane_state->fb) != get_mem_type(fb))) + drm_warn_once(state->dev, + "[PLANE:%d:%s] async flip with non-fast update\n", + plane->base.id, plane->name); ++ + bundle->flip_addrs[planes_count].flip_immediate = + crtc->state->async_flip && + acrtc_state->update_type == UPDATE_TYPE_FAST && +@@ -10040,6 +10042,11 @@ static int amdgpu_dm_atomic_check(struct + + /* Remove exiting planes if they are modified */ + for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { ++ if (old_plane_state->fb && new_plane_state->fb && ++ get_mem_type(old_plane_state->fb) != ++ get_mem_type(new_plane_state->fb)) ++ lock_and_validation_needed = true; ++ + ret = dm_update_plane_state(dc, state, plane, + old_plane_state, + new_plane_state, +@@ -10287,9 +10294,20 @@ static int amdgpu_dm_atomic_check(struct + struct dm_crtc_state *dm_new_crtc_state = + to_dm_crtc_state(new_crtc_state); + ++ /* ++ * Only allow async flips for fast updates that don't change ++ * the FB pitch, the DCC state, rotation, etc. ++ */ ++ if (new_crtc_state->async_flip && lock_and_validation_needed) { ++ drm_dbg_atomic(crtc->dev, ++ "[CRTC:%d:%s] async flips are only supported for fast updates\n", ++ crtc->base.id, crtc->name); ++ ret = -EINVAL; ++ goto fail; ++ } ++ + dm_new_crtc_state->update_type = lock_and_validation_needed ? +- UPDATE_TYPE_FULL : +- UPDATE_TYPE_FAST; ++ UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; + } + + /* Must be success */ +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +@@ -398,18 +398,6 @@ static int dm_crtc_helper_atomic_check(s + return -EINVAL; + } + +- /* +- * Only allow async flips for fast updates that don't change the FB +- * pitch, the DCC state, rotation, etc. +- */ +- if (crtc_state->async_flip && +- dm_crtc_state->update_type != UPDATE_TYPE_FAST) { +- drm_dbg_atomic(crtc->dev, +- "[CRTC:%d:%s] async flips are only supported for fast updates\n", +- crtc->base.id, crtc->name); +- return -EINVAL; +- } +- + /* In some use cases, like reset, no stream is attached */ + if (!dm_crtc_state->stream) + return 0; diff --git a/queue-6.5/series b/queue-6.5/series new file mode 100644 index 00000000000..44756e69dae --- /dev/null +++ b/queue-6.5/series @@ -0,0 +1,3 @@ +drm-amd-display-ensure-async-flips-are-only-accepted-for-fast-updates.patch +cpufreq-intel_pstate-set-stale-cpu-frequency-to-minimum.patch +tpm-enable-hwrng-only-for-pluton-on-amd-cpus.patch diff --git a/queue-6.5/tpm-enable-hwrng-only-for-pluton-on-amd-cpus.patch b/queue-6.5/tpm-enable-hwrng-only-for-pluton-on-amd-cpus.patch new file mode 100644 index 00000000000..55aef4c0e37 --- /dev/null +++ b/queue-6.5/tpm-enable-hwrng-only-for-pluton-on-amd-cpus.patch @@ -0,0 +1,82 @@ +From 8f7f35e5aa6f2182eabcfa3abef4d898a48e9aa8 Mon Sep 17 00:00:00 2001 +From: Jarkko Sakkinen +Date: Mon, 4 Sep 2023 21:12:10 +0300 +Subject: tpm: Enable hwrng only for Pluton on AMD CPUs + +From: Jarkko Sakkinen + +commit 8f7f35e5aa6f2182eabcfa3abef4d898a48e9aa8 upstream. + +The vendor check introduced by commit 554b841d4703 ("tpm: Disable RNG for +all AMD fTPMs") doesn't work properly on a number of Intel fTPMs. On the +reported systems the TPM doesn't reply at bootup and returns back the +command code. This makes the TPM fail probe on Lenovo Legion Y540 laptop. + +Since only Microsoft Pluton is the only known combination of AMD CPU and +fTPM from other vendor, disable hwrng otherwise. In order to make sysadmin +aware of this, print also info message to the klog. + +Cc: stable@vger.kernel.org +Fixes: 554b841d4703 ("tpm: Disable RNG for all AMD fTPMs") +Reported-by: Todd Brandt +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217804 +Reported-by: Patrick Steinhardt +Reported-by: Raymond Jay Golo +Reported-by: Ronan Pigott +Reviewed-by: Jerry Snitselaar +Signed-off-by: Jarkko Sakkinen +Cc: Thorsten Leemhuis +Signed-off-by: Greg Kroah-Hartman +--- + drivers/char/tpm/tpm_crb.c | 33 ++++++++------------------------- + 1 file changed, 8 insertions(+), 25 deletions(-) + +--- a/drivers/char/tpm/tpm_crb.c ++++ b/drivers/char/tpm/tpm_crb.c +@@ -463,28 +463,6 @@ static bool crb_req_canceled(struct tpm_ + return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE; + } + +-static int crb_check_flags(struct tpm_chip *chip) +-{ +- u32 val; +- int ret; +- +- ret = crb_request_locality(chip, 0); +- if (ret) +- return ret; +- +- ret = tpm2_get_tpm_pt(chip, TPM2_PT_MANUFACTURER, &val, NULL); +- if (ret) +- goto release; +- +- if (val == 0x414D4400U /* AMD */) +- chip->flags |= TPM_CHIP_FLAG_HWRNG_DISABLED; +- +-release: +- crb_relinquish_locality(chip, 0); +- +- return ret; +-} +- + static const struct tpm_class_ops tpm_crb = { + .flags = TPM_OPS_AUTO_STARTUP, + .status = crb_status, +@@ -826,9 +804,14 @@ static int crb_acpi_add(struct acpi_devi + if (rc) + goto out; + +- rc = crb_check_flags(chip); +- if (rc) +- goto out; ++#ifdef CONFIG_X86 ++ /* A quirk for https://www.amd.com/en/support/kb/faq/pa-410 */ ++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && ++ priv->sm != ACPI_TPM2_COMMAND_BUFFER_WITH_PLUTON) { ++ dev_info(dev, "Disabling hwrng\n"); ++ chip->flags |= TPM_CHIP_FLAG_HWRNG_DISABLED; ++ } ++#endif /* CONFIG_X86 */ + + rc = tpm_chip_register(chip); +