From: Stepan Ionichev Date: Wed, 13 May 2026 10:13:32 +0000 (+0500) Subject: iio: adc: ad7192: fix GPOCON register access annotation X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=b049fb4081527c8d52834c46cef38c0bb65468ed;p=thirdparty%2Fkernel%2Fstable.git iio: adc: ad7192: fix GPOCON register access annotation The comment next to AD7192_REG_GPOCON marks the register as RO, but the AD7192 datasheet (Rev. A, page 24, GPOCON REGISTER) says: "The GPOCON register is an 8-bit register from which data can be read or to which data can be written." The driver itself uses ad_sd_write_reg() against this register in ad7192_show_scale() / write paths to control the bridge power-down switch and digital outputs, which matches the RW datasheet description. Update the comment to RW so it does not mislead future readers. Signed-off-by: Stepan Ionichev Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index ba27614c89b4..caf4473ad643 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -39,7 +39,7 @@ #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ -#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ +#define AD7192_REG_GPOCON 5 /* GPOCON Register (RW, 8-bit) */ #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ /* (AD7792)/24-bit (AD7192)) */ #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */