From: Oleg Endo Date: Sun, 29 Sep 2024 12:33:29 +0000 (+0900) Subject: SH: Tighten memory predicates and constraints X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=b13642241df8f18dfd2e32f7e550d53dbea6e55f;p=thirdparty%2Fgcc.git SH: Tighten memory predicates and constraints In particular, reject invalid hard-regs for memory address registers when using LRA. Unfortunately we need to distingquish between old reload and LRA behaviors for the transitional period. LRA seems to require stricter predicates and constraints. gcc/ChangeLog: PR target/55212 * config/sh/predicates.md (simple_mem_operand): Use 'satisfies_constraint_Sra'. (post_inc_mem, pre_dec_mem): Use 'satisfies_constraint_Rab'. * config/sh/constraints.md (Rab, Rai, Sgb): New constraints. (Sua, Sdd, Snd, Ssd, Sbv, Sra, Ara, Add): Use Rab and Rai constraints. * config/sh/sync.md (atomic_mem_operand_0, atomic_mem_operand_1): Reject GBR addresses when hard-llcs atomic mode is enabled. --- diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md index 51569cdfd2d..7b476dc6c38 100644 --- a/gcc/config/sh/constraints.md +++ b/gcc/config/sh/constraints.md @@ -45,8 +45,10 @@ ;; H: Floating point 1 ;; Q: pc relative load operand ;; Rxx: reserved for exotic register classes. +;; Rab: address base register +;; Rai: address index register ;; Sxx: extra memory constraints -;; Sua: unaligned memory address +;; Sua: simple or post-inc address (for unaligned load) ;; Sbv: QImode address without displacement ;; Sbw: QImode address with 12 bit displacement ;; Snd: address without displacement @@ -260,16 +262,36 @@ (match_test "~ival == 64") (match_test "~ival == 128")))) +;; FIXME: LRA and reload behavior differs in memory constraint handling. +;; For LRA memory address constraints need to narrow the register type +;; restrictions. It seems the address RTX validation is done slightly +;; differently. Remove the non-LRA paths eventually. +(define_constraint "Rab" + "@internal address base register constraint" + (ior (and (match_test "sh_lra_p ()") + (match_test "MAYBE_BASE_REGISTER_RTX_P (op, false)")) + (and (match_test "!sh_lra_p ()") + (match_code "reg")))) + +(define_constraint "Rai" + "@internal address index register constraint" + (ior (and (match_test "sh_lra_p ()") + (match_test "MAYBE_INDEX_REGISTER_RTX_P (op, false)")) + (and (match_test "!sh_lra_p ()") + (match_code "reg")))) + (define_memory_constraint "Sua" - "@internal" - (and (match_test "memory_operand (op, GET_MODE (op))") - (match_test "GET_CODE (XEXP (op, 0)) != PLUS"))) + "A memory reference that allows simple register or post-inc addressing." + (and (match_code "mem") + (ior (match_test "satisfies_constraint_Rab (XEXP (op, 0))") + (and (match_code "post_inc" "0") + (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))"))))) (define_memory_constraint "Sdd" "A memory reference that uses displacement addressing." (and (match_code "mem") (match_code "plus" "0") - (match_code "reg" "00") + (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))") (match_code "const_int" "01"))) (define_memory_constraint "Snd" @@ -281,19 +303,28 @@ "A memory reference that uses index addressing." (and (match_code "mem") (match_code "plus" "0") - (match_code "reg" "00") - (match_code "reg" "01"))) + (ior (and (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))") + (match_test "satisfies_constraint_Rai (XEXP (XEXP (op, 0), 1))")) + (and (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 1))") + (match_test "satisfies_constraint_Rai (XEXP (XEXP (op, 0), 0))"))))) (define_memory_constraint "Ssd" "A memory reference that excludes index and displacement addressing." - (and (match_code "mem") - (match_test "! satisfies_constraint_Sid (op)") - (match_test "! satisfies_constraint_Sdd (op)"))) + (ior (and (match_code "mem") + (match_test "! sh_lra_p ()") + (match_test "! satisfies_constraint_Sid (op)") + (match_test "! satisfies_constraint_Sdd (op)")) + (and (match_code "mem") + (match_test "sh_lra_p ()") + (ior (match_test "satisfies_constraint_Rab (XEXP (op, 0))") + (and (ior (match_code "pre_dec" "0") (match_code "post_inc" "0")) + (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))")))))) (define_memory_constraint "Sbv" "A memory reference, as used in SH2A bclr.b, bset.b, etc." - (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") - (match_test "REG_P (XEXP (op, 0))"))) + (and (match_code "mem") + (match_test "GET_MODE (op) == QImode") + (match_test "satisfies_constraint_Rab (XEXP (op, 0))"))) (define_memory_constraint "Sbw" "A memory reference, as used in SH2A bclr.b, bset.b, etc." @@ -304,13 +335,17 @@ (define_memory_constraint "Sra" "A memory reference that uses simple register addressing." (and (match_code "mem") - (match_code "reg" "0"))) + (match_test "satisfies_constraint_Rab (XEXP (op, 0))"))) + +(define_memory_constraint "Sgb" + "A memory renference that uses GBR addressing." + (match_test "gbr_address_mem (op, GET_MODE (op))")) (define_memory_constraint "Ara" "A memory reference that uses simple register addressing suitable for gusa atomic operations." (and (match_code "mem") - (match_code "reg" "0") + (match_test "satisfies_constraint_Rab (XEXP (op, 0))") (match_test "REGNO (XEXP (op, 0)) != SP_REG"))) (define_memory_constraint "Add" @@ -319,6 +354,6 @@ (and (match_code "mem") (match_test "GET_MODE (op) == SImode") (match_code "plus" "0") - (match_code "reg" "00") + (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))") (match_code "const_int" "01") (match_test "REGNO (XEXP (XEXP (op, 0), 0)) != SP_REG"))) diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index f7051087213..6964833a479 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -208,8 +208,7 @@ ;; Returns 1 if OP is a simple register address. (define_predicate "simple_mem_operand" (and (match_code "mem") - (match_code "reg" "0") - (match_test "arith_reg_operand (XEXP (op, 0), SImode)"))) + (match_test "satisfies_constraint_Sra (op)"))) ;; Returns 1 if OP is a valid displacement address. (define_predicate "displacement_mem_operand" @@ -239,13 +238,13 @@ (define_predicate "post_inc_mem" (and (match_code "mem") (match_code "post_inc" "0") - (match_code "reg" "00"))) + (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))"))) ;; Returns true if OP is a pre-decrement addressing mode memory reference. (define_predicate "pre_dec_mem" (and (match_code "mem") (match_code "pre_dec" "0") - (match_code "reg" "00"))) + (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))"))) ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn. (define_predicate "zero_extend_movu_operand" diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md index b0b412b3d9d..6025b7716cc 100644 --- a/gcc/config/sh/sync.md +++ b/gcc/config/sh/sync.md @@ -217,7 +217,9 @@ (and (match_test "mode == SImode") (and (match_test "!TARGET_ATOMIC_HARD_LLCS") (match_test "!TARGET_SH4A || TARGET_ATOMIC_STRICT")) - (match_operand 0 "short_displacement_mem_operand"))))) + (match_operand 0 "short_displacement_mem_operand"))) + (ior (match_test "!TARGET_ATOMIC_HARD_LLCS") + (not (match_operand 0 "gbr_address_mem"))))) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "arith_reg_dest") ;; bool success output @@ -715,7 +717,9 @@ && TARGET_SH4A && !TARGET_ATOMIC_STRICT && mode != SImode")) (ior (match_operand 0 "short_displacement_mem_operand") - (match_operand 0 "gbr_address_mem")))))) + (match_operand 0 "gbr_address_mem")))) + (ior (match_test "!TARGET_ATOMIC_HARD_LLCS") + (not (match_operand 0 "gbr_address_mem"))))) (define_expand "atomic_fetch_" [(set (match_operand:QIHISI 0 "arith_reg_dest")