From: Sasha Levin Date: Fri, 13 Sep 2024 14:11:20 +0000 (-0400) Subject: Fixes for 6.10 X-Git-Tag: v6.1.111~35 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=b4c79abe6a1b61a94f03d00f2a1914684e8ca2ea;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.10 Signed-off-by: Sasha Levin --- diff --git a/queue-6.10/arm64-dts-rockchip-fix-pmic-interrupt-pin-in-pinctrl.patch b/queue-6.10/arm64-dts-rockchip-fix-pmic-interrupt-pin-in-pinctrl.patch new file mode 100644 index 00000000000..35f29e961ee --- /dev/null +++ b/queue-6.10/arm64-dts-rockchip-fix-pmic-interrupt-pin-in-pinctrl.patch @@ -0,0 +1,37 @@ +From 3568f45cf5f4325afa269a7d05028b4bfdc226af Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 22 Jul 2024 18:52:16 +0900 +Subject: arm64: dts: rockchip: fix PMIC interrupt pin in pinctrl for ROCK Pi E + +From: FUKAUMI Naoki + +[ Upstream commit c623e9daf60a0275d623ce054601550e54987f5b ] + +use GPIO0_A2 as PMIC interrupt pin in pinctrl. +(I forgot to fix this part in previous commit.) + +Fixes: 02afd3d5b9fa ("arm64: dts: rockchip: fix PMIC interrupt pin on ROCK Pi E") +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20240722095216.1656081-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +index a608a219543e..3e08e2fd0a78 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +@@ -387,7 +387,7 @@ led_pin: led-pin { + + pmic { + pmic_int_l: pmic-int-l { +- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +-- +2.43.0 + diff --git a/queue-6.10/clk-sophgo-using-bug-instead-of-unreachable-in-mmux_.patch b/queue-6.10/clk-sophgo-using-bug-instead-of-unreachable-in-mmux_.patch new file mode 100644 index 00000000000..99e6ad1c41d --- /dev/null +++ b/queue-6.10/clk-sophgo-using-bug-instead-of-unreachable-in-mmux_.patch @@ -0,0 +1,42 @@ +From 2ad93e5a777abc3e3629c402c47f7ecb441d847e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 9 Jul 2024 14:36:38 +0800 +Subject: clk/sophgo: Using BUG() instead of unreachable() in + mmux_get_parent_id() + +From: Li Qiang + +[ Upstream commit 1f7a04a0e673c19cc10bf4039047e11367ac5735 ] + +In general it's a good idea to avoid using bare unreachable() because it +introduces undefined behavior in compiled code. but it caused a compilation warning, +Using BUG() instead of unreachable() to resolve compilation warnings. + +Fixes the following warnings: + drivers/clk/sophgo/clk-cv18xx-ip.o: warning: objtool: mmux_round_rate() falls through to next function bypass_div_round_rate() + +Fixes: 80fd61ec46124 ("clk: sophgo: Add clock support for CV1800 SoC") +Signed-off-by: Li Qiang +Link: https://lore.kernel.org/r/c8e66d51f880127549e2a3e623be6787f62b310d.1720506143.git.liqiang01@kylinos.cn +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/sophgo/clk-cv18xx-ip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/sophgo/clk-cv18xx-ip.c b/drivers/clk/sophgo/clk-cv18xx-ip.c +index 805f561725ae..b186e64d4813 100644 +--- a/drivers/clk/sophgo/clk-cv18xx-ip.c ++++ b/drivers/clk/sophgo/clk-cv18xx-ip.c +@@ -613,7 +613,7 @@ static u8 mmux_get_parent_id(struct cv1800_clk_mmux *mmux) + return i; + } + +- unreachable(); ++ BUG(); + } + + static int mmux_enable(struct clk_hw *hw) +-- +2.43.0 + diff --git a/queue-6.10/cxl-core-fix-incorrect-vendor-debug-uuid-define.patch b/queue-6.10/cxl-core-fix-incorrect-vendor-debug-uuid-define.patch new file mode 100644 index 00000000000..64a73ec668b --- /dev/null +++ b/queue-6.10/cxl-core-fix-incorrect-vendor-debug-uuid-define.patch @@ -0,0 +1,52 @@ +From 383b5ab82b46a124d9af787824daac4ee0dbf955 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Jul 2024 10:31:12 +0800 +Subject: cxl/core: Fix incorrect vendor debug UUID define + +From: peng guo + +[ Upstream commit 8ecef8e01a08c7e3e4ffc8f08d9f9663984f334b ] + +When user send a mbox command whose opcode is CXL_MBOX_OP_CLEAR_LOG and +the in_payload is normal vendor debug log UUID according to +the CXL specification cxl_payload_from_user_allowed() will return +false unexpectedly, Sending mbox cmd operation fails and the kernel +log will print: +Clear Log: input payload not allowed. + +All CXL devices that support a debug log shall support the Vendor Debug +Log to allow the log to be accessed through a common host driver, for any +device, all versions of the CXL specification define the same value with +Log Identifier of: 5e1819d9-11a9-400c-811f-d60719403d86 + +Refer to CXL spec r3.1 Table 8-71 + +Fix the definition value of DEFINE_CXL_VENDOR_DEBUG_UUID to match the +CXL specification. + +Fixes: 472b1ce6e9d6 ("cxl/mem: Enable commands via CEL") +Signed-off-by: peng guo +Reviewed-by: Alison Schofield +Link: https://patch.msgid.link/20240710023112.8063-1-engguopeng@buaa.edu.cn +Signed-off-by: Dave Jiang +Signed-off-by: Sasha Levin +--- + drivers/cxl/cxlmem.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h +index af8169ccdbc0..feb1106559d2 100644 +--- a/drivers/cxl/cxlmem.h ++++ b/drivers/cxl/cxlmem.h +@@ -563,7 +563,7 @@ enum cxl_opcode { + 0x3b, 0x3f, 0x17) + + #define DEFINE_CXL_VENDOR_DEBUG_UUID \ +- UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ ++ UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ + 0x40, 0x3d, 0x86) + + struct cxl_mbox_get_supported_logs { +-- +2.43.0 + diff --git a/queue-6.10/cxl-restore-xor-d-position-bits-during-address-trans.patch b/queue-6.10/cxl-restore-xor-d-position-bits-during-address-trans.patch new file mode 100644 index 00000000000..e4dafbd0ada --- /dev/null +++ b/queue-6.10/cxl-restore-xor-d-position-bits-during-address-trans.patch @@ -0,0 +1,191 @@ +From 510fd8693077cd94c412c78cbed6eb899c03036c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 2 Jul 2024 22:29:50 -0700 +Subject: cxl: Restore XOR'd position bits during address translation + +From: Alison Schofield + +[ Upstream commit 3b2fedcd75e3991e77c2a8c3ebcab0ea68b2d69d ] + +When a device reports a DPA in events like poison, general_media, +and dram, the driver translates that DPA back to an HPA. Presently, +the CXL driver translation only considers the Modulo position and +will report the wrong HPA for XOR configured root decoders. + +Add a helper function that restores the XOR'd bits during DPA->HPA +address translation. Plumb a root decoder callback to the new helper +when XOR interleave arithmetic is in use. For Modulo arithmetic, just +let the callback be NULL - as in no extra work required. + +Upon completion of a DPA->HPA translation a couple of checks are +performed on the result. One simply confirms that the calculated +HPA is within the address range of the region. That test is useful +for both Modulo and XOR interleave arithmetic decodes. + +A second check confirms that the HPA is within an expected chunk +based on the endpoints position in the region and the region +granularity. An XOR decode disrupts the Modulo pattern making the +chunk check useless. + +To align the checks with the proper decode, pull the region range +check inline and use the helper to do the chunk check for Modulo +decodes only. + +A cxl-test unit test is posted for upstream review here: +https://lore.kernel.org/20240624210644.495563-1-alison.schofield@intel.com/ + +Fixes: 28a3ae4ff66c ("cxl/trace: Add an HPA to cxl_poison trace events") +Signed-off-by: Alison Schofield +Tested-by: Diego Garcia Rodriguez +Reviewed-by: Dan Williams +Link: https://patch.msgid.link/1a1ac880d9f889bd6384e657e810431b9a0a72e5.1719980933.git.alison.schofield@intel.com +Signed-off-by: Dave Jiang +Signed-off-by: Sasha Levin +--- + drivers/cxl/acpi.c | 40 +++++++++++++++++++++++++++++++++++++++ + drivers/cxl/core/region.c | 23 +++++++++++++--------- + drivers/cxl/cxl.h | 3 +++ + 3 files changed, 57 insertions(+), 9 deletions(-) + +diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c +index 571069863c62..6b6ae9c81368 100644 +--- a/drivers/cxl/acpi.c ++++ b/drivers/cxl/acpi.c +@@ -74,6 +74,43 @@ static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos) + return cxlrd->cxlsd.target[n]; + } + ++static u64 cxl_xor_hpa_to_spa(struct cxl_root_decoder *cxlrd, u64 hpa) ++{ ++ struct cxl_cxims_data *cximsd = cxlrd->platform_data; ++ int hbiw = cxlrd->cxlsd.nr_targets; ++ u64 val; ++ int pos; ++ ++ /* No xormaps for host bridge interleave ways of 1 or 3 */ ++ if (hbiw == 1 || hbiw == 3) ++ return hpa; ++ ++ /* ++ * For root decoders using xormaps (hbiw: 2,4,6,8,12,16) restore ++ * the position bit to its value before the xormap was applied at ++ * HPA->DPA translation. ++ * ++ * pos is the lowest set bit in an XORMAP ++ * val is the XORALLBITS(HPA & XORMAP) ++ * ++ * XORALLBITS: The CXL spec (3.1 Table 9-22) defines XORALLBITS ++ * as an operation that outputs a single bit by XORing all the ++ * bits in the input (hpa & xormap). Implement XORALLBITS using ++ * hweight64(). If the hamming weight is even the XOR of those ++ * bits results in val==0, if odd the XOR result is val==1. ++ */ ++ ++ for (int i = 0; i < cximsd->nr_maps; i++) { ++ if (!cximsd->xormaps[i]) ++ continue; ++ pos = __ffs(cximsd->xormaps[i]); ++ val = (hweight64(hpa & cximsd->xormaps[i]) & 1); ++ hpa = (hpa & ~(1ULL << pos)) | (val << pos); ++ } ++ ++ return hpa; ++} ++ + struct cxl_cxims_context { + struct device *dev; + struct cxl_root_decoder *cxlrd; +@@ -434,6 +471,9 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, + + cxlrd->qos_class = cfmws->qtg_id; + ++ if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) ++ cxlrd->hpa_to_spa = cxl_xor_hpa_to_spa; ++ + rc = cxl_decoder_add(cxld, target_map); + if (rc) + return rc; +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index 0e30e0a29d40..3345ccbade0b 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -2830,20 +2830,13 @@ struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) + return ctx.cxlr; + } + +-static bool cxl_is_hpa_in_range(u64 hpa, struct cxl_region *cxlr, int pos) ++static bool cxl_is_hpa_in_chunk(u64 hpa, struct cxl_region *cxlr, int pos) + { + struct cxl_region_params *p = &cxlr->params; + int gran = p->interleave_granularity; + int ways = p->interleave_ways; + u64 offset; + +- /* Is the hpa within this region at all */ +- if (hpa < p->res->start || hpa > p->res->end) { +- dev_dbg(&cxlr->dev, +- "Addr trans fail: hpa 0x%llx not in region\n", hpa); +- return false; +- } +- + /* Is the hpa in an expected chunk for its pos(-ition) */ + offset = hpa - p->res->start; + offset = do_div(offset, gran * ways); +@@ -2859,6 +2852,7 @@ static bool cxl_is_hpa_in_range(u64 hpa, struct cxl_region *cxlr, int pos) + static u64 cxl_dpa_to_hpa(u64 dpa, struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled) + { ++ struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); + u64 dpa_offset, hpa_offset, bits_upper, mask_upper, hpa; + struct cxl_region_params *p = &cxlr->params; + int pos = cxled->pos; +@@ -2898,7 +2892,18 @@ static u64 cxl_dpa_to_hpa(u64 dpa, struct cxl_region *cxlr, + /* Apply the hpa_offset to the region base address */ + hpa = hpa_offset + p->res->start; + +- if (!cxl_is_hpa_in_range(hpa, cxlr, cxled->pos)) ++ /* Root decoder translation overrides typical modulo decode */ ++ if (cxlrd->hpa_to_spa) ++ hpa = cxlrd->hpa_to_spa(cxlrd, hpa); ++ ++ if (hpa < p->res->start || hpa > p->res->end) { ++ dev_dbg(&cxlr->dev, ++ "Addr trans fail: hpa 0x%llx not in region\n", hpa); ++ return ULLONG_MAX; ++ } ++ ++ /* Simple chunk check, by pos & gran, only applies to modulo decodes */ ++ if (!cxlrd->hpa_to_spa && (!cxl_is_hpa_in_chunk(hpa, cxlr, pos))) + return ULLONG_MAX; + + return hpa; +diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h +index a6613a6f8923..b8e16e8697e2 100644 +--- a/drivers/cxl/cxl.h ++++ b/drivers/cxl/cxl.h +@@ -436,12 +436,14 @@ struct cxl_switch_decoder { + struct cxl_root_decoder; + typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, + int pos); ++typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa); + + /** + * struct cxl_root_decoder - Static platform CXL address decoder + * @res: host / parent resource for region allocations + * @region_id: region id for next region provisioning event + * @calc_hb: which host bridge covers the n'th position by granularity ++ * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address + * @platform_data: platform specific configuration data + * @range_lock: sync region autodiscovery by address range + * @qos_class: QoS performance class cookie +@@ -451,6 +453,7 @@ struct cxl_root_decoder { + struct resource *res; + atomic_t region_id; + cxl_calc_hb_fn calc_hb; ++ cxl_hpa_to_spa_fn hpa_to_spa; + void *platform_data; + struct mutex range_lock; + int qos_class; +-- +2.43.0 + diff --git a/queue-6.10/drm-amd-display-disable-error-correction-if-it-s-not.patch b/queue-6.10/drm-amd-display-disable-error-correction-if-it-s-not.patch new file mode 100644 index 00000000000..2c196089781 --- /dev/null +++ b/queue-6.10/drm-amd-display-disable-error-correction-if-it-s-not.patch @@ -0,0 +1,110 @@ +From b4fc4b4809f66cec5ce1a7eeb72db6f48f6eb0fb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 12 Apr 2024 09:51:29 +0800 +Subject: drm/amd/display: Disable error correction if it's not supported + +From: Cruise + +[ Upstream commit a8ac994cf0693a1ce59410995594e56124a1c79f ] + +[Why] +Error correction was enabled in a monitor which doesn't support. + +[How] +Disable error correction if it's not supported + +Reviewed-by: Wenjing Liu +Acked-by: Aurabindo Pillai +Signed-off-by: Cruise +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Stable-dep-of: a8baec4623ae ("drm/amd/display: Fix FEC_READY write on DP LT") +Signed-off-by: Sasha Levin +--- + .../display/dc/link/protocols/link_dp_phy.c | 47 +++++++++---------- + 1 file changed, 21 insertions(+), 26 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +index 2fa4e64e2430..5cbf5f93e584 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +@@ -147,32 +147,27 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource + + link_enc = link_enc_cfg_get_link_enc(link); + ASSERT(link_enc); ++ if (link_enc->funcs->fec_set_ready == NULL) ++ return DC_NOT_SUPPORTED; + +- if (!dp_should_enable_fec(link)) +- return status; +- +- if (link_enc->funcs->fec_set_ready && +- link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { +- if (ready) { ++ if (ready && dp_should_enable_fec(link)) { ++ if (link->fec_state == dc_link_fec_not_ready) { + fec_config = 1; +- status = core_link_write_dpcd(link, +- DP_FEC_CONFIGURATION, +- &fec_config, +- sizeof(fec_config)); ++ ++ status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION, ++ &fec_config, sizeof(fec_config)); ++ + if (status == DC_OK) { + link_enc->funcs->fec_set_ready(link_enc, true); + link->fec_state = dc_link_fec_ready; +- } else { +- link_enc->funcs->fec_set_ready(link_enc, false); +- link->fec_state = dc_link_fec_not_ready; +- dm_error("dpcd write failed to set fec_ready"); + } +- } else if (link->fec_state == dc_link_fec_ready) { ++ } ++ } else { ++ if (link->fec_state == dc_link_fec_ready) { + fec_config = 0; +- status = core_link_write_dpcd(link, +- DP_FEC_CONFIGURATION, +- &fec_config, +- sizeof(fec_config)); ++ core_link_write_dpcd(link, DP_FEC_CONFIGURATION, ++ &fec_config, sizeof(fec_config)); ++ + link_enc->funcs->fec_set_ready(link_enc, false); + link->fec_state = dc_link_fec_not_ready; + } +@@ -187,14 +182,12 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) + + link_enc = link_enc_cfg_get_link_enc(link); + ASSERT(link_enc); +- +- if (!dp_should_enable_fec(link)) ++ if (link_enc->funcs->fec_set_enable == NULL) + return; + +- if (link_enc->funcs->fec_set_enable && +- link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { +- if (link->fec_state == dc_link_fec_ready && enable) { +- /* Accord to DP spec, FEC enable sequence can first ++ if (enable && dp_should_enable_fec(link)) { ++ if (link->fec_state == dc_link_fec_ready) { ++ /* According to DP spec, FEC enable sequence can first + * be transmitted anytime after 1000 LL codes have + * been transmitted on the link after link training + * completion. Using 1 lane RBR should have the maximum +@@ -204,7 +197,9 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) + udelay(7); + link_enc->funcs->fec_set_enable(link_enc, true); + link->fec_state = dc_link_fec_enabled; +- } else if (link->fec_state == dc_link_fec_enabled && !enable) { ++ } ++ } else { ++ if (link->fec_state == dc_link_fec_enabled) { + link_enc->funcs->fec_set_enable(link_enc, false); + link->fec_state = dc_link_fec_ready; + } +-- +2.43.0 + diff --git a/queue-6.10/drm-amd-display-fix-fec_ready-write-on-dp-lt.patch b/queue-6.10/drm-amd-display-fix-fec_ready-write-on-dp-lt.patch new file mode 100644 index 00000000000..0ba8f4c9687 --- /dev/null +++ b/queue-6.10/drm-amd-display-fix-fec_ready-write-on-dp-lt.patch @@ -0,0 +1,57 @@ +From 6cdfa0e0b0d746003c42c76e59c89488f2745480 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 17 Apr 2024 14:21:28 -0400 +Subject: drm/amd/display: Fix FEC_READY write on DP LT + +From: Ilya Bakoulin + +[ Upstream commit a8baec4623aedf36d50767627f6eae5ebf07c6fb ] + +[Why/How] +We can miss writing FEC_READY in some cases before LT start, which +violates DP spec. Remove the condition guarding the DPCD write so that +the write happens unconditionally. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Wenjing Liu +Acked-by: Wayne Lin +Signed-off-by: Ilya Bakoulin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + .../amd/display/dc/link/protocols/link_dp_phy.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +index 5cbf5f93e584..bafa52a0165a 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +@@ -151,16 +151,14 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource + return DC_NOT_SUPPORTED; + + if (ready && dp_should_enable_fec(link)) { +- if (link->fec_state == dc_link_fec_not_ready) { +- fec_config = 1; ++ fec_config = 1; + +- status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION, +- &fec_config, sizeof(fec_config)); ++ status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION, ++ &fec_config, sizeof(fec_config)); + +- if (status == DC_OK) { +- link_enc->funcs->fec_set_ready(link_enc, true); +- link->fec_state = dc_link_fec_ready; +- } ++ if (status == DC_OK) { ++ link_enc->funcs->fec_set_ready(link_enc, true); ++ link->fec_state = dc_link_fec_ready; + } + } else { + if (link->fec_state == dc_link_fec_ready) { +-- +2.43.0 + diff --git a/queue-6.10/eeprom-digsy_mtc-fix-93xx46-driver-probe-failure.patch b/queue-6.10/eeprom-digsy_mtc-fix-93xx46-driver-probe-failure.patch new file mode 100644 index 00000000000..172c962af7c --- /dev/null +++ b/queue-6.10/eeprom-digsy_mtc-fix-93xx46-driver-probe-failure.patch @@ -0,0 +1,39 @@ +From 71a1052fb65c78410d97852140d113d886c1c514 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 May 2024 21:46:55 +0300 +Subject: eeprom: digsy_mtc: Fix 93xx46 driver probe failure + +From: Andy Shevchenko + +[ Upstream commit 2b82641ad0620b2d71dc05024b20f82db7e1c0b6 ] + +The update to support other (bigger) types of EEPROMs broke +the driver loading due to removal of the default size. + +Fix this by adding the respective (new) flag to the platform data. + +Fixes: 14374fbb3f06 ("misc: eeprom_93xx46: Add new 93c56 and 93c66 compatible strings") +Signed-off-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20240508184905.2102633-3-andriy.shevchenko@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/misc/eeprom/digsy_mtc_eeprom.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/misc/eeprom/digsy_mtc_eeprom.c b/drivers/misc/eeprom/digsy_mtc_eeprom.c +index f1f766b70965..4eddc5ba1af9 100644 +--- a/drivers/misc/eeprom/digsy_mtc_eeprom.c ++++ b/drivers/misc/eeprom/digsy_mtc_eeprom.c +@@ -42,7 +42,7 @@ static void digsy_mtc_op_finish(void *p) + } + + struct eeprom_93xx46_platform_data digsy_mtc_eeprom_data = { +- .flags = EE_ADDR8, ++ .flags = EE_ADDR8 | EE_SIZE1K, + .prepare = digsy_mtc_op_prepare, + .finish = digsy_mtc_op_finish, + }; +-- +2.43.0 + diff --git a/queue-6.10/firmware-qcom-uefisecapp-fix-deadlock-in-qcuefi_acqu.patch b/queue-6.10/firmware-qcom-uefisecapp-fix-deadlock-in-qcuefi_acqu.patch new file mode 100644 index 00000000000..73298bd0086 --- /dev/null +++ b/queue-6.10/firmware-qcom-uefisecapp-fix-deadlock-in-qcuefi_acqu.patch @@ -0,0 +1,42 @@ +From 4e6a5d1fbf008235386aec275171b02d81126ae9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Aug 2024 22:23:04 +0300 +Subject: firmware: qcom: uefisecapp: Fix deadlock in qcuefi_acquire() + +From: Dan Carpenter + +[ Upstream commit db213b0cfe3268d8b1d382b3bcc999c687a2567f ] + +If the __qcuefi pointer is not set, then in the original code, we would +hold onto the lock. That means that if we tried to set it later, then +it would cause a deadlock. Drop the lock on the error path. That's +what all the callers are expecting. + +Fixes: 759e7a2b62eb ("firmware: Add support for Qualcomm UEFI Secure Application") +Signed-off-by: Dan Carpenter +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/19829bc4-1b6f-47f7-847a-e90c25749e40@stanley.mountain +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/firmware/qcom/qcom_qseecom_uefisecapp.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c b/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c +index bc550ad0dbe0..68b2c09ed22c 100644 +--- a/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c ++++ b/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c +@@ -786,6 +786,10 @@ static int qcuefi_set_reference(struct qcuefi_client *qcuefi) + static struct qcuefi_client *qcuefi_acquire(void) + { + mutex_lock(&__qcuefi_lock); ++ if (!__qcuefi) { ++ mutex_unlock(&__qcuefi_lock); ++ return NULL; ++ } + return __qcuefi; + } + +-- +2.43.0 + diff --git a/queue-6.10/riscv-dts-starfive-jh7110-common-fix-lower-rate-of-c.patch b/queue-6.10/riscv-dts-starfive-jh7110-common-fix-lower-rate-of-c.patch new file mode 100644 index 00000000000..8f1d9c021db --- /dev/null +++ b/queue-6.10/riscv-dts-starfive-jh7110-common-fix-lower-rate-of-c.patch @@ -0,0 +1,46 @@ +From 67b60bf9777bd340c7179adb5376dcdd3f0c260c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Aug 2024 16:04:30 +0800 +Subject: riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by + setting PLL0 rate to 1.5GHz + +From: Xingyu Wu + +[ Upstream commit 61f2e8a3a94175dbbaad6a54f381b2a505324610 ] + +CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. +But now PLL0 rate is 1GHz and the cpu frequency loads become +250/333/500/1000MHz in fact. + +The PLL0 rate should be default set to 1.5GHz and set the +cpu_core rate to 500MHz in safe. + +Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") +Signed-off-by: Xingyu Wu +Reviewed-by: Hal Feng +Signed-off-by: Conor Dooley +Signed-off-by: Sasha Levin +--- + arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +index 68d16717db8c..51d85f447626 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +@@ -354,6 +354,12 @@ spi_dev0: spi@0 { + }; + }; + ++&syscrg { ++ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, ++ <&pllclk JH7110_PLLCLK_PLL0_OUT>; ++ assigned-clock-rates = <500000000>, <1500000000>; ++}; ++ + &sysgpio { + i2c0_pins: i2c0-0 { + i2c-pins { +-- +2.43.0 + diff --git a/queue-6.10/selftests-bpf-support-sock_stream-in-unix_inet_redir.patch b/queue-6.10/selftests-bpf-support-sock_stream-in-unix_inet_redir.patch new file mode 100644 index 00000000000..b5206cc4f96 --- /dev/null +++ b/queue-6.10/selftests-bpf-support-sock_stream-in-unix_inet_redir.patch @@ -0,0 +1,48 @@ +From 536e890e14030cc8e6797b01ef21a67252b09f42 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 13 Jul 2024 21:41:39 +0200 +Subject: selftests/bpf: Support SOCK_STREAM in unix_inet_redir_to_connected() + +From: Michal Luczaj + +[ Upstream commit 1b0ad43177c097d38b967b99c2b71d8be28b0223 ] + +Function ignores the AF_UNIX socket type argument, SOCK_DGRAM is hardcoded. +Fix to respect the argument provided. + +Fixes: 75e0e27db6cf ("selftest/bpf: Change udp to inet in some function names") +Suggested-by: Jakub Sitnicki +Signed-off-by: Michal Luczaj +Signed-off-by: Daniel Borkmann +Tested-by: Jakub Sitnicki +Reviewed-by: Jakub Sitnicki +Link: https://lore.kernel.org/bpf/20240713200218.2140950-3-mhal@rbox.co +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/bpf/prog_tests/sockmap_listen.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/tools/testing/selftests/bpf/prog_tests/sockmap_listen.c b/tools/testing/selftests/bpf/prog_tests/sockmap_listen.c +index e91b59366030..c075d376fcab 100644 +--- a/tools/testing/selftests/bpf/prog_tests/sockmap_listen.c ++++ b/tools/testing/selftests/bpf/prog_tests/sockmap_listen.c +@@ -1828,7 +1828,7 @@ static void unix_inet_redir_to_connected(int family, int type, + if (err) + return; + +- if (socketpair(AF_UNIX, SOCK_DGRAM | SOCK_NONBLOCK, 0, sfd)) ++ if (socketpair(AF_UNIX, type | SOCK_NONBLOCK, 0, sfd)) + goto close_cli0; + c1 = sfd[0], p1 = sfd[1]; + +@@ -1840,7 +1840,6 @@ static void unix_inet_redir_to_connected(int family, int type, + close_cli0: + xclose(c0); + xclose(p0); +- + } + + static void unix_inet_skb_redir_to_connected(struct test_sockmap_listen *skel, +-- +2.43.0 + diff --git a/queue-6.10/series b/queue-6.10/series index 653e3066781..bebc4bcdd49 100644 --- a/queue-6.10/series +++ b/queue-6.10/series @@ -56,3 +56,13 @@ mm-avoid-leaving-partial-pfn-mappings-around-in-error-case.patch bcachefs-fix-bch2_extents_match-false-positive.patch bcachefs-revert-lockless-buffered-io-path.patch bcachefs-don-t-delete-open-files-in-online-fsck.patch +arm64-dts-rockchip-fix-pmic-interrupt-pin-in-pinctrl.patch +firmware-qcom-uefisecapp-fix-deadlock-in-qcuefi_acqu.patch +riscv-dts-starfive-jh7110-common-fix-lower-rate-of-c.patch +drm-amd-display-disable-error-correction-if-it-s-not.patch +drm-amd-display-fix-fec_ready-write-on-dp-lt.patch +eeprom-digsy_mtc-fix-93xx46-driver-probe-failure.patch +clk-sophgo-using-bug-instead-of-unreachable-in-mmux_.patch +cxl-core-fix-incorrect-vendor-debug-uuid-define.patch +cxl-restore-xor-d-position-bits-during-address-trans.patch +selftests-bpf-support-sock_stream-in-unix_inet_redir.patch