From: Ulrich Drepper <drepper@redhat.com>
Date: Tue, 22 Jul 2003 00:14:36 +0000 (+0000)
Subject: Update.
X-Git-Tag: cvs/glibc-2_3_3~433
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=b72e048f190dba7202751d8c27508f82e015ebad;p=thirdparty%2Fglibc.git

Update.

	* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask.
	* sysdeps/i386/fpu/feenablxcpt.c: Likewise.
	* sysdeps/i386/fpu/feholdexcpt.c: Likewise.
	* sysdeps/i386/fpu/fesetround.c: Likewise.
	* sysdeps/i386/fpu/ftestexcept.c: Likewise.
---

diff --git a/ChangeLog b/ChangeLog
index ed5bdf40c3c..87cc44553ef 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -6,6 +6,12 @@
 	which has undefined symbols.
 	* elf/Makefile: Likewise.
 
+	* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask.
+	* sysdeps/i386/fpu/feenablxcpt.c: Likewise.
+	* sysdeps/i386/fpu/feholdexcpt.c: Likewise.
+	* sysdeps/i386/fpu/fesetround.c: Likewise.
+	* sysdeps/i386/fpu/ftestexcept.c: Likewise.
+
 2003-07-21  HJ Lu  <hongjiu.lu@intel.com>
 
 	* elf/ldconfig.c (search_dir): Treat symlink as regular file
diff --git a/sysdeps/i386/fpu/fedisblxcpt.c b/sysdeps/i386/fpu/fedisblxcpt.c
index 6e337d388ab..ef3dd9a44cb 100644
--- a/sysdeps/i386/fpu/fedisblxcpt.c
+++ b/sysdeps/i386/fpu/fedisblxcpt.c
@@ -39,7 +39,7 @@ fedisableexcept (int excepts)
   __asm__ ("fldcw %0" : : "m" (*&new_exc));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+  if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
     {
       unsigned int xnew_exc;
 
diff --git a/sysdeps/i386/fpu/feenablxcpt.c b/sysdeps/i386/fpu/feenablxcpt.c
index 0f841caad93..a000d02d357 100644
--- a/sysdeps/i386/fpu/feenablxcpt.c
+++ b/sysdeps/i386/fpu/feenablxcpt.c
@@ -39,7 +39,7 @@ feenableexcept (int excepts)
   __asm__ ("fldcw %0" : : "m" (*&new_exc));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+  if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
     {
       unsigned int xnew_exc;
 
diff --git a/sysdeps/i386/fpu/feholdexcpt.c b/sysdeps/i386/fpu/feholdexcpt.c
index 5d622ada15a..2d6cc0d4424 100644
--- a/sysdeps/i386/fpu/feholdexcpt.c
+++ b/sysdeps/i386/fpu/feholdexcpt.c
@@ -36,7 +36,7 @@ feholdexcept (fenv_t *envp)
   __asm__ ("fldcw %0" : : "m" (*&work));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+  if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
     {
       unsigned int xwork;
 
diff --git a/sysdeps/i386/fpu/fesetround.c b/sysdeps/i386/fpu/fesetround.c
index fae74d33b62..fe9889ffa00 100644
--- a/sysdeps/i386/fpu/fesetround.c
+++ b/sysdeps/i386/fpu/fesetround.c
@@ -38,7 +38,7 @@ fesetround (int round)
   __asm__ ("fldcw %0" : : "m" (*&cw));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+  if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
     {
       unsigned int xcw;
 
diff --git a/sysdeps/i386/fpu/ftestexcept.c b/sysdeps/i386/fpu/ftestexcept.c
index e449571c042..f82b3553529 100644
--- a/sysdeps/i386/fpu/ftestexcept.c
+++ b/sysdeps/i386/fpu/ftestexcept.c
@@ -33,7 +33,7 @@ fetestexcept (int excepts)
   __asm__ ("fnstsw %0" : "=a" (temp));
 
   /* If the CPU supports SSE we test the MXCSR as well.  */
-  if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+  if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
     __asm__ ("stmxcsr %0" : "=m" (*&xtemp));
 
   return (temp | xtemp) & excepts & FE_ALL_EXCEPT;