From: Sasha Levin Date: Sun, 25 Aug 2024 23:46:18 +0000 (-0400) Subject: Fixes for 6.6 X-Git-Tag: v6.1.107~65 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=b8fd2cee14d0fbd0a465e218761bc968c21deed6;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.6 Signed-off-by: Sasha Levin --- diff --git a/queue-6.6/drm-msm-dp-fix-the-max-supported-bpp-logic.patch b/queue-6.6/drm-msm-dp-fix-the-max-supported-bpp-logic.patch new file mode 100644 index 00000000000..64b036a6331 --- /dev/null +++ b/queue-6.6/drm-msm-dp-fix-the-max-supported-bpp-logic.patch @@ -0,0 +1,91 @@ +From 41ba0fcb0b1d9253a27812c29ef85df8ae7bd126 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Aug 2024 13:20:08 -0700 +Subject: drm/msm/dp: fix the max supported bpp logic + +From: Abhinav Kumar + +[ Upstream commit d19d5b8d8f6dab942ce5ddbcf34bf7275e778250 ] + +Fix the dp_panel_get_supported_bpp() API to return the minimum +supported bpp correctly for relevant cases and use this API +to correct the behavior of DP driver which hard-codes the max supported +bpp to 30. + +This is incorrect because the number of lanes and max data rate +supported by the lanes need to be taken into account. + +Replace the hardcoded limit with the appropriate math which accounts +for the accurate number of lanes and max data rate. + +changes in v2: + - Fix the dp_panel_get_supported_bpp() and use it + - Drop the max_t usage as dp_panel_get_supported_bpp() already + returns the min_bpp correctly now + +changes in v3: + - replace min_t with just min as all params are u32 + +Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") +Reported-by: Dmitry Baryshkov +Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/43 +Tested-by: Dmitry Baryshkov # SM8350-HDK +Reviewed-by: Stephen Boyd +Patchwork: https://patchwork.freedesktop.org/patch/607073/ +Link: https://lore.kernel.org/r/20240805202009.1120981-1-quic_abhinavk@quicinc.com +Signed-off-by: Stephen Boyd +Signed-off-by: Abhinav Kumar +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/dp/dp_panel.c | 19 ++++++++++--------- + 1 file changed, 10 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c +index 86a8e06c7a60f..d26589eb8b218 100644 +--- a/drivers/gpu/drm/msm/dp/dp_panel.c ++++ b/drivers/gpu/drm/msm/dp/dp_panel.c +@@ -136,22 +136,22 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) + static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel, + u32 mode_edid_bpp, u32 mode_pclk_khz) + { +- struct dp_link_info *link_info; ++ const struct dp_link_info *link_info; + const u32 max_supported_bpp = 30, min_supported_bpp = 18; +- u32 bpp = 0, data_rate_khz = 0; ++ u32 bpp, data_rate_khz; + +- bpp = min_t(u32, mode_edid_bpp, max_supported_bpp); ++ bpp = min(mode_edid_bpp, max_supported_bpp); + + link_info = &dp_panel->link_info; + data_rate_khz = link_info->num_lanes * link_info->rate * 8; + +- while (bpp > min_supported_bpp) { ++ do { + if (mode_pclk_khz * bpp <= data_rate_khz) +- break; ++ return bpp; + bpp -= 6; +- } ++ } while (bpp > min_supported_bpp); + +- return bpp; ++ return min_supported_bpp; + } + + static int dp_panel_update_modes(struct drm_connector *connector, +@@ -444,8 +444,9 @@ int dp_panel_init_panel_info(struct dp_panel *dp_panel) + drm_mode->clock); + drm_dbg_dp(panel->drm_dev, "bpp = %d\n", dp_panel->dp_mode.bpp); + +- dp_panel->dp_mode.bpp = max_t(u32, 18, +- min_t(u32, dp_panel->dp_mode.bpp, 30)); ++ dp_panel->dp_mode.bpp = dp_panel_get_mode_bpp(dp_panel, dp_panel->dp_mode.bpp, ++ dp_panel->dp_mode.drm_mode.clock); ++ + drm_dbg_dp(panel->drm_dev, "updated bpp = %d\n", + dp_panel->dp_mode.bpp); + +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dp-reset-the-link-phy-params-before-link-tra.patch b/queue-6.6/drm-msm-dp-reset-the-link-phy-params-before-link-tra.patch new file mode 100644 index 00000000000..5940776e6c6 --- /dev/null +++ b/queue-6.6/drm-msm-dp-reset-the-link-phy-params-before-link-tra.patch @@ -0,0 +1,42 @@ +From eab5e948bc224528fc432ea7fdd01b47fe4a7eb7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Jul 2024 15:04:50 -0700 +Subject: drm/msm/dp: reset the link phy params before link training + +From: Abhinav Kumar + +[ Upstream commit 319aca883bfa1b85ee08411541b51b9a934ac858 ] + +Before re-starting link training reset the link phy params namely +the pre-emphasis and voltage swing levels otherwise the next +link training begins at the previously cached levels which can result +in link training failures. + +Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") +Reviewed-by: Dmitry Baryshkov +Tested-by: Dmitry Baryshkov # SM8350-HDK +Reviewed-by: Stephen Boyd +Patchwork: https://patchwork.freedesktop.org/patch/605946/ +Link: https://lore.kernel.org/r/20240725220450.131245-1-quic_abhinavk@quicinc.com +Signed-off-by: Abhinav Kumar +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c +index 780e9747be1fb..7472dfd631b83 100644 +--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c ++++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c +@@ -1253,6 +1253,8 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, + link_info.rate = ctrl->link->link_params.rate; + link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; + ++ dp_link_reset_phy_params_vx_px(ctrl->link); ++ + dp_aux_link_configure(ctrl->aux, &link_info); + + if (drm_dp_max_downspread(dpcd)) +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-capture-snapshot-on-the-first-commit_don.patch b/queue-6.6/drm-msm-dpu-capture-snapshot-on-the-first-commit_don.patch new file mode 100644 index 00000000000..67a70a48570 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-capture-snapshot-on-the-first-commit_don.patch @@ -0,0 +1,67 @@ +From aad3f4816a308e6a46158280dc09414848c2a463 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Feb 2024 04:28:01 +0200 +Subject: drm/msm/dpu: capture snapshot on the first commit_done timeout + +From: Dmitry Baryshkov + +[ Upstream commit 4be445f5b6b6810baf397b2d159bd07c3573fd75 ] + +In order to debug commit_done timeouts, capture the devcoredump state +when the first timeout occurs after the encoder has been enabled. + +Reviewed-by: Abhinav Kumar +Signed-off-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/579850/ +Link: https://lore.kernel.org/r/20240226-fd-dpu-debug-timeout-v4-3-51eec83dde23@linaro.org +Stable-dep-of: aedf02e46eb5 ("drm/msm/dpu: move dpu_encoder's connector assignment to atomic_enable()") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +index ba60997350890..0c57588044641 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +@@ -124,6 +124,8 @@ enum dpu_enc_rc_states { + * @base: drm_encoder base class for registration with DRM + * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes + * @enabled: True if the encoder is active, protected by enc_lock ++ * @commit_done_timedout: True if there has been a timeout on commit after ++ * enabling the encoder. + * @num_phys_encs: Actual number of physical encoders contained. + * @phys_encs: Container of physical encoders managed. + * @cur_master: Pointer to the current master in this mode. Optimization +@@ -172,6 +174,7 @@ struct dpu_encoder_virt { + spinlock_t enc_spinlock; + + bool enabled; ++ bool commit_done_timedout; + + unsigned int num_phys_encs; + struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; +@@ -1210,6 +1213,9 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, + dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); + + mutex_lock(&dpu_enc->enc_lock); ++ ++ dpu_enc->commit_done_timedout = false; ++ + cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; + + trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, +@@ -2446,6 +2452,10 @@ int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) + DPU_ATRACE_BEGIN("wait_for_commit_done"); + ret = phys->ops.wait_for_commit_done(phys); + DPU_ATRACE_END("wait_for_commit_done"); ++ if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) { ++ dpu_enc->commit_done_timedout = true; ++ msm_disp_snapshot_state(drm_enc->dev); ++ } + if (ret) + return ret; + } +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-cleanup-fb-if-dpu_format_populate_layout.patch b/queue-6.6/drm-msm-dpu-cleanup-fb-if-dpu_format_populate_layout.patch new file mode 100644 index 00000000000..b645add46c8 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-cleanup-fb-if-dpu_format_populate_layout.patch @@ -0,0 +1,70 @@ +From cd7442e4763909b6b539deabe56c6cf06e9ede40 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jun 2024 00:13:41 +0300 +Subject: drm/msm/dpu: cleanup FB if dpu_format_populate_layout fails + +From: Dmitry Baryshkov + +[ Upstream commit bfa1a6283be390947d3649c482e5167186a37016 ] + +If the dpu_format_populate_layout() fails, then FB is prepared, but not +cleaned up. This ends up leaking the pin_count on the GEM object and +causes a splat during DRM file closure: + +msm_obj->pin_count +WARNING: CPU: 2 PID: 569 at drivers/gpu/drm/msm/msm_gem.c:121 update_lru_locked+0xc4/0xcc +[...] +Call trace: + update_lru_locked+0xc4/0xcc + put_pages+0xac/0x100 + msm_gem_free_object+0x138/0x180 + drm_gem_object_free+0x1c/0x30 + drm_gem_object_handle_put_unlocked+0x108/0x10c + drm_gem_object_release_handle+0x58/0x70 + idr_for_each+0x68/0xec + drm_gem_release+0x28/0x40 + drm_file_free+0x174/0x234 + drm_release+0xb0/0x160 + __fput+0xc0/0x2c8 + __fput_sync+0x50/0x5c + __arm64_sys_close+0x38/0x7c + invoke_syscall+0x48/0x118 + el0_svc_common.constprop.0+0x40/0xe0 + do_el0_svc+0x1c/0x28 + el0_svc+0x4c/0x120 + el0t_64_sync_handler+0x100/0x12c + el0t_64_sync+0x190/0x194 +irq event stamp: 129818 +hardirqs last enabled at (129817): [] console_unlock+0x118/0x124 +hardirqs last disabled at (129818): [] el1_dbg+0x24/0x8c +softirqs last enabled at (129808): [] handle_softirqs+0x4c8/0x4e8 +softirqs last disabled at (129785): [] __do_softirq+0x14/0x20 + +Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/600714/ +Link: https://lore.kernel.org/r/20240625-dpu-mode-config-width-v5-1-501d984d634f@linaro.org +Signed-off-by: Abhinav Kumar +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +index 0be195f9149c5..5ffbf131e1e80 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +@@ -679,6 +679,9 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, + new_state->fb, &layout); + if (ret) { + DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); ++ if (pstate->aspace) ++ msm_framebuffer_cleanup(new_state->fb, pstate->aspace, ++ pstate->needs_dirtyfb); + return ret; + } + +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-don-t-play-tricks-with-debug-macros.patch b/queue-6.6/drm-msm-dpu-don-t-play-tricks-with-debug-macros.patch new file mode 100644 index 00000000000..8ac714fb7b0 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-don-t-play-tricks-with-debug-macros.patch @@ -0,0 +1,66 @@ +From ce60e7bb30566b0a758c5c1c2e00ca30f08e0914 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Aug 2024 22:47:34 +0300 +Subject: drm/msm/dpu: don't play tricks with debug macros + +From: Dmitry Baryshkov + +[ Upstream commit df24373435f5899a2a98b7d377479c8d4376613b ] + +DPU debugging macros need to be converted to a proper drm_debug_* +macros, however this is a going an intrusive patch, not suitable for a +fix. Wire DPU_DEBUG and DPU_DEBUG_DRIVER to always use DRM_DEBUG_DRIVER +to make sure that DPU debugging messages always end up in the drm debug +messages and are controlled via the usual drm.debug mask. + +I don't think that it is a good idea for a generic DPU_DEBUG macro to be +tied to DRM_UT_KMS. It is used to report a debug message from driver, so by +default it should go to the DRM_UT_DRIVER channel. While refactoring +debug macros later on we might end up with particular messages going to +ATOMIC or KMS, but DRIVER should be the default. + +Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/606932/ +Link: https://lore.kernel.org/r/20240802-dpu-fix-wb-v2-2-7eac9eb8e895@linaro.org +Signed-off-by: Abhinav Kumar +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 14 ++------------ + 1 file changed, 2 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +index f5473d4dea92f..8cb3cf842c52c 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +@@ -31,24 +31,14 @@ + * @fmt: Pointer to format string + */ + #define DPU_DEBUG(fmt, ...) \ +- do { \ +- if (drm_debug_enabled(DRM_UT_KMS)) \ +- DRM_DEBUG(fmt, ##__VA_ARGS__); \ +- else \ +- pr_debug(fmt, ##__VA_ARGS__); \ +- } while (0) ++ DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__) + + /** + * DPU_DEBUG_DRIVER - macro for hardware driver logging + * @fmt: Pointer to format string + */ + #define DPU_DEBUG_DRIVER(fmt, ...) \ +- do { \ +- if (drm_debug_enabled(DRM_UT_DRIVER)) \ +- DRM_ERROR(fmt, ##__VA_ARGS__); \ +- else \ +- pr_debug(fmt, ##__VA_ARGS__); \ +- } while (0) ++ DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__) + + #define DPU_ERROR(fmt, ...) pr_err("[dpu error]" fmt, ##__VA_ARGS__) + #define DPU_ERROR_RATELIMITED(fmt, ...) pr_err_ratelimited("[dpu error]" fmt, ##__VA_ARGS__) +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-drop-msm_enc_vblank-support.patch b/queue-6.6/drm-msm-dpu-drop-msm_enc_vblank-support.patch new file mode 100644 index 00000000000..ca4abba9856 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-drop-msm_enc_vblank-support.patch @@ -0,0 +1,159 @@ +From 3e60b4adb7636b693e47d9c21447d079433c93c6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 4 Oct 2023 06:19:03 +0300 +Subject: drm/msm/dpu: drop MSM_ENC_VBLANK support + +From: Dmitry Baryshkov + +[ Upstream commit a08935fc859b22884dcb6b5126d3a986467101ce ] + +There are no in-kernel users of MSM_ENC_VBLANK wait type. Drop it +together with the corresponding wait_for_vblank callback. + +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/560701/ +Link: https://lore.kernel.org/r/20231004031903.518223-1-dmitry.baryshkov@linaro.org +Signed-off-by: Dmitry Baryshkov +Stable-dep-of: aedf02e46eb5 ("drm/msm/dpu: move dpu_encoder's connector assignment to atomic_enable()") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 -- + .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 1 - + .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 28 ------------------- + .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +++--- + drivers/gpu/drm/msm/msm_drv.h | 2 -- + 5 files changed, 4 insertions(+), 39 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +index 781adb5e2c595..57001543dc220 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +@@ -2441,9 +2441,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, + case MSM_ENC_TX_COMPLETE: + fn_wait = phys->ops.wait_for_tx_complete; + break; +- case MSM_ENC_VBLANK: +- fn_wait = phys->ops.wait_for_vblank; +- break; + default: + DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", + event); +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +index 99997707b0ee9..57a3598f2a303 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +@@ -106,7 +106,6 @@ struct dpu_encoder_phys_ops { + int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable); + int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); + int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); +- int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc); + void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc); + void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); + void (*trigger_start)(struct dpu_encoder_phys *phys_enc); +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +index 548be5cf07be8..83a804ebf8d7e 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +@@ -681,33 +681,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( + return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); + } + +-static int dpu_encoder_phys_cmd_wait_for_vblank( +- struct dpu_encoder_phys *phys_enc) +-{ +- int rc = 0; +- struct dpu_encoder_phys_cmd *cmd_enc; +- struct dpu_encoder_wait_info wait_info; +- +- cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); +- +- /* only required for master controller */ +- if (!dpu_encoder_phys_cmd_is_master(phys_enc)) +- return rc; +- +- wait_info.wq = &cmd_enc->pending_vblank_wq; +- wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt; +- wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; +- +- atomic_inc(&cmd_enc->pending_vblank_cnt); +- +- rc = dpu_encoder_helper_wait_for_irq(phys_enc, +- phys_enc->irq[INTR_IDX_RDPTR], +- dpu_encoder_phys_cmd_te_rd_ptr_irq, +- &wait_info); +- +- return rc; +-} +- + static void dpu_encoder_phys_cmd_handle_post_kickoff( + struct dpu_encoder_phys *phys_enc) + { +@@ -735,7 +708,6 @@ static void dpu_encoder_phys_cmd_init_ops( + ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done; + ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff; + ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete; +- ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank; + ops->trigger_start = dpu_encoder_phys_cmd_trigger_start; + ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush; + ops->irq_control = dpu_encoder_phys_cmd_irq_control; +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +index ab26e21871235..daaf0e6047538 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +@@ -443,7 +443,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) + phys_enc->enable_state = DPU_ENC_ENABLING; + } + +-static int dpu_encoder_phys_vid_wait_for_vblank( ++static int dpu_encoder_phys_vid_wait_for_tx_complete( + struct dpu_encoder_phys *phys_enc) + { + struct dpu_encoder_wait_info wait_info; +@@ -557,7 +557,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) + * scanout buffer) don't latch properly.. + */ + if (dpu_encoder_phys_vid_is_master(phys_enc)) { +- ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); ++ ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc); + if (ret) { + atomic_set(&phys_enc->pending_kickoff_cnt, 0); + DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", +@@ -577,7 +577,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) + spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); + dpu_encoder_phys_inc_pending(phys_enc); + spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); +- ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); ++ ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc); + if (ret) { + atomic_set(&phys_enc->pending_kickoff_cnt, 0); + DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", +@@ -682,8 +682,7 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) + ops->disable = dpu_encoder_phys_vid_disable; + ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; + ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; +- ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank; +- ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank; ++ ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete; + ops->irq_control = dpu_encoder_phys_vid_irq_control; + ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; + ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; +diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h +index 02fd6c7d0bb7b..182543c92770c 100644 +--- a/drivers/gpu/drm/msm/msm_drv.h ++++ b/drivers/gpu/drm/msm/msm_drv.h +@@ -78,12 +78,10 @@ enum msm_dsi_controller { + * enum msm_event_wait - type of HW events to wait for + * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW + * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel +- * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) + */ + enum msm_event_wait { + MSM_ENC_COMMIT_DONE = 0, + MSM_ENC_TX_COMPLETE, +- MSM_ENC_VBLANK, + }; + + /** +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-move-dpu_encoder-s-connector-assignment-.patch b/queue-6.6/drm-msm-dpu-move-dpu_encoder-s-connector-assignment-.patch new file mode 100644 index 00000000000..e7e6e2c696f --- /dev/null +++ b/queue-6.6/drm-msm-dpu-move-dpu_encoder-s-connector-assignment-.patch @@ -0,0 +1,61 @@ +From ee6d3cfad99625f4f3f592f70dc657e5c3879111 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 31 Jul 2024 12:17:22 -0700 +Subject: drm/msm/dpu: move dpu_encoder's connector assignment to + atomic_enable() + +From: Abhinav Kumar + +[ Upstream commit aedf02e46eb549dac8db4821a6b9f0c6bf6e3990 ] + +For cases where the crtc's connectors_changed was set without enable/active +getting toggled , there is an atomic_enable() call followed by an +atomic_disable() but without an atomic_mode_set(). + +This results in a NULL ptr access for the dpu_encoder_get_drm_fmt() call in +the atomic_enable() as the dpu_encoder's connector was cleared in the +atomic_disable() but not re-assigned as there was no atomic_mode_set() call. + +Fix the NULL ptr access by moving the assignment for atomic_enable() and also +use drm_atomic_get_new_connector_for_encoder() to get the connector from +the atomic_state. + +Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") +Reported-by: Dmitry Baryshkov +Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/59 +Suggested-by: Dmitry Baryshkov +Reviewed-by: Dmitry Baryshkov +Tested-by: Dmitry Baryshkov # SM8350-HDK +Patchwork: https://patchwork.freedesktop.org/patch/606729/ +Link: https://lore.kernel.org/r/20240731191723.3050932-1-quic_abhinavk@quicinc.com +Signed-off-by: Abhinav Kumar +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +index 0c57588044641..6262ec5e40204 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +@@ -1119,8 +1119,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, + + cstate->num_mixers = num_lm; + +- dpu_enc->connector = conn_state->connector; +- + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + +@@ -1216,6 +1214,8 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, + + dpu_enc->commit_done_timedout = false; + ++ dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); ++ + cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; + + trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-split-dpu_encoder_wait_for_event-into-tw.patch b/queue-6.6/drm-msm-dpu-split-dpu_encoder_wait_for_event-into-tw.patch new file mode 100644 index 00000000000..68860852417 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-split-dpu_encoder_wait_for_event-into-tw.patch @@ -0,0 +1,194 @@ +From ce83fa108ec370e06a40a5a4cc5f3d0e5cce6e80 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Feb 2024 04:28:00 +0200 +Subject: drm/msm/dpu: split dpu_encoder_wait_for_event into two functions + +From: Dmitry Baryshkov + +[ Upstream commit d72a3d35b7ef5a3c0260462f130fa3dd7576aa2f ] + +Stop multiplexing several events via the dpu_encoder_wait_for_event() +function. Split it into two distinct functions two allow separate +handling of those events. + +Reviewed-by: Abhinav Kumar +Signed-off-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/579848/ +Link: https://lore.kernel.org/r/20240226-fd-dpu-debug-timeout-v4-2-51eec83dde23@linaro.org +Stable-dep-of: aedf02e46eb5 ("drm/msm/dpu: move dpu_encoder's connector assignment to atomic_enable()") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 70 +++++++++++++++------ + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 +------ + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- + drivers/gpu/drm/msm/msm_drv.h | 10 --- + 4 files changed, 55 insertions(+), 49 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +index 57001543dc220..ba60997350890 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +@@ -1265,7 +1265,7 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, + trace_dpu_enc_disable(DRMID(drm_enc)); + + /* wait for idle */ +- dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); ++ dpu_encoder_wait_for_tx_complete(drm_enc); + + dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); + +@@ -2417,10 +2417,18 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, + return ERR_PTR(ret); + } + +-int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, +- enum msm_event_wait event) ++/** ++ * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state ++ * @drm_enc: encoder pointer ++ * ++ * Wait for hardware to have flushed the current pending changes to hardware at ++ * a vblank or CTL_START. Physical encoders will map this differently depending ++ * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START. ++ * ++ * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise ++ */ ++int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) + { +- int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; + struct dpu_encoder_virt *dpu_enc = NULL; + int i, ret = 0; + +@@ -2434,23 +2442,47 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + +- switch (event) { +- case MSM_ENC_COMMIT_DONE: +- fn_wait = phys->ops.wait_for_commit_done; +- break; +- case MSM_ENC_TX_COMPLETE: +- fn_wait = phys->ops.wait_for_tx_complete; +- break; +- default: +- DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", +- event); +- return -EINVAL; ++ if (phys->ops.wait_for_commit_done) { ++ DPU_ATRACE_BEGIN("wait_for_commit_done"); ++ ret = phys->ops.wait_for_commit_done(phys); ++ DPU_ATRACE_END("wait_for_commit_done"); ++ if (ret) ++ return ret; + } ++ } ++ ++ return ret; ++} ++ ++/** ++ * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel ++ * @drm_enc: encoder pointer ++ * ++ * Wait for the hardware to transfer all the pixels to the panel. Physical ++ * encoders will map this differently depending on the type: vid mode -> vsync_irq, ++ * cmd mode -> pp_done. ++ * ++ * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise ++ */ ++int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc) ++{ ++ struct dpu_encoder_virt *dpu_enc = NULL; ++ int i, ret = 0; ++ ++ if (!drm_enc) { ++ DPU_ERROR("invalid encoder\n"); ++ return -EINVAL; ++ } ++ dpu_enc = to_dpu_encoder_virt(drm_enc); ++ DPU_DEBUG_ENC(dpu_enc, "\n"); ++ ++ for (i = 0; i < dpu_enc->num_phys_encs; i++) { ++ struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + +- if (fn_wait) { +- DPU_ATRACE_BEGIN("wait_for_completion_event"); +- ret = fn_wait(phys); +- DPU_ATRACE_END("wait_for_completion_event"); ++ if (phys->ops.wait_for_tx_complete) { ++ DPU_ATRACE_BEGIN("wait_for_tx_complete"); ++ ret = phys->ops.wait_for_tx_complete(phys); ++ DPU_ATRACE_END("wait_for_tx_complete"); + if (ret) + return ret; + } +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +index fe6b1d312a742..0c928d1876e4a 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +@@ -93,25 +93,9 @@ void dpu_encoder_kickoff(struct drm_encoder *encoder); + */ + int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time); + +-/** +- * dpu_encoder_wait_for_event - Waits for encoder events +- * @encoder: encoder pointer +- * @event: event to wait for +- * MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending +- * frames to hardware at a vblank or ctl_start +- * Encoders will map this differently depending on the +- * panel type. +- * vid mode -> vsync_irq +- * cmd mode -> ctl_start +- * MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to +- * the panel. Encoders will map this differently +- * depending on the panel type. +- * vid mode -> vsync_irq +- * cmd mode -> pp_done +- * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise +- */ +-int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder, +- enum msm_event_wait event); ++int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder); ++ ++int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder); + + /* + * dpu_encoder_get_intf_mode - get interface mode of the given encoder +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +index aa6ba2cf4b840..6ba289e04b3b2 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +@@ -490,7 +490,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, + * mode panels. This may be a no-op for command mode panels. + */ + trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); +- ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); ++ ret = dpu_encoder_wait_for_commit_done(encoder); + if (ret && ret != -EWOULDBLOCK) { + DPU_ERROR("wait for commit done returned %d\n", ret); + break; +diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h +index 182543c92770c..48e1a8c6942c9 100644 +--- a/drivers/gpu/drm/msm/msm_drv.h ++++ b/drivers/gpu/drm/msm/msm_drv.h +@@ -74,16 +74,6 @@ enum msm_dsi_controller { + #define MSM_GPU_MAX_RINGS 4 + #define MAX_H_TILES_PER_DISPLAY 2 + +-/** +- * enum msm_event_wait - type of HW events to wait for +- * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW +- * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel +- */ +-enum msm_event_wait { +- MSM_ENC_COMMIT_DONE = 0, +- MSM_ENC_TX_COMPLETE, +-}; +- + /** + * struct msm_display_topology - defines a display topology pipeline + * @num_lm: number of layer mixers used +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-take-plane-rotation-into-account-for-wid.patch b/queue-6.6/drm-msm-dpu-take-plane-rotation-into-account-for-wid.patch new file mode 100644 index 00000000000..ca267ac2550 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-take-plane-rotation-into-account-for-wid.patch @@ -0,0 +1,62 @@ +From 2f964beeebb47a4de9a745c9dbfc4b177ecc3abd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 27 Jun 2024 00:45:57 +0300 +Subject: drm/msm/dpu: take plane rotation into account for wide planes + +From: Dmitry Baryshkov + +[ Upstream commit d3a785e4f983f523380e023d8a05fb6d04402957 ] + +Take into account the plane rotation and flipping when calculating src +positions for the wide plane parts. + +This is not an issue yet, because rotation is only supported for the +UBWC planes and wide UBWC planes are rejected anyway because in parallel +multirect case only the half of the usual width is supported for tiled +formats. However it's better to fix this now rather than stumbling upon +it later. + +Fixes: 80e8ae3b38ab ("drm/msm/dpu: add support for wide planes") +Reviewed-by: Abhinav Kumar +Signed-off-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/601059/ +Link: https://lore.kernel.org/r/20240627-dpu-virtual-wide-v5-3-5efb90cbb8be@linaro.org +Signed-off-by: Abhinav Kumar +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +index 3c2a8c0ddaf76..637f50a8d42e6 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +@@ -865,6 +865,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, + + max_linewidth = pdpu->catalog->caps->max_linewidth; + ++ drm_rect_rotate(&pipe_cfg->src_rect, ++ new_plane_state->fb->width, new_plane_state->fb->height, ++ new_plane_state->rotation); ++ + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { + /* +@@ -914,6 +918,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, + r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; + } + ++ drm_rect_rotate_inv(&pipe_cfg->src_rect, ++ new_plane_state->fb->width, new_plane_state->fb->height, ++ new_plane_state->rotation); ++ if (r_pipe->sspp) ++ drm_rect_rotate_inv(&r_pipe_cfg->src_rect, ++ new_plane_state->fb->width, new_plane_state->fb->height, ++ new_plane_state->rotation); ++ + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); + if (ret) + return ret; +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-try-multirect-based-on-mdp-clock-limits.patch b/queue-6.6/drm-msm-dpu-try-multirect-based-on-mdp-clock-limits.patch new file mode 100644 index 00000000000..b63b6177094 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-try-multirect-based-on-mdp-clock-limits.patch @@ -0,0 +1,71 @@ +From 0fe2ecb54387f041345ae129e21d49c2b0fa0347 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Sep 2023 15:16:27 -0700 +Subject: drm/msm/dpu: try multirect based on mdp clock limits + +From: Abhinav Kumar + +[ Upstream commit e6c0de5f445091d250b75dabc4c60dd2643b8c98 ] + +It's certainly possible that for large resolutions a single DPU SSPP +cannot process the image without exceeding the MDP clock limits but +it can still process it in multirect mode because the source rectangles +will get divided and can fall within the MDP clock limits. + +If the SSPP cannot process the image even in multirect mode, then it +will be rejected in dpu_plane_atomic_check_pipe(). + +Hence try using multirect for resolutions which cannot be processed +by a single SSPP without exceeding the MDP clock limits. + +changes in v2: + - use crtc_state's adjusted_mode instead of mode + - fix the UBWC condition to check maxlinewidth + +Signed-off-by: Abhinav Kumar +Reviewed-by: Dmitry Baryshkov +Tested-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/556817/ +Link: https://lore.kernel.org/r/20230911221627.9569-2-quic_abhinavk@quicinc.com +Signed-off-by: Dmitry Baryshkov +Stable-dep-of: d3a785e4f983 ("drm/msm/dpu: take plane rotation into account for wide planes") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +index 5ffbf131e1e80..3c2a8c0ddaf76 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +@@ -795,6 +795,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, + plane); + int ret = 0, min_scale; + struct dpu_plane *pdpu = to_dpu_plane(plane); ++ struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); ++ u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; +@@ -863,14 +865,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, + + max_linewidth = pdpu->catalog->caps->max_linewidth; + +- if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { ++ if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || ++ _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { + /* + * In parallel multirect case only the half of the usual width + * is supported for tiled formats. If we are here, we know that + * full width is more than max_linewidth, thus each rect is + * wider than allowed. + */ +- if (DPU_FORMAT_IS_UBWC(fmt)) { ++ if (DPU_FORMAT_IS_UBWC(fmt) && ++ drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-dpu-use-drmm-managed-allocation-for-dpu_enco.patch b/queue-6.6/drm-msm-dpu-use-drmm-managed-allocation-for-dpu_enco.patch new file mode 100644 index 00000000000..2dff9687048 --- /dev/null +++ b/queue-6.6/drm-msm-dpu-use-drmm-managed-allocation-for-dpu_enco.patch @@ -0,0 +1,278 @@ +From 07af66faee296ef84e890216ef0b722afa7d410d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 00:18:43 +0300 +Subject: drm/msm/dpu: use drmm-managed allocation for dpu_encoder_phys + +From: Dmitry Baryshkov + +[ Upstream commit 73169b45e1ed296b4357a694f5fa586ac0643ac1 ] + +Change struct allocation of encoder's phys backend data to use +drmm_kzalloc(). This removes the need to perform any actions on encoder +destruction. + +Reviewed-by: Jessica Zhang +Signed-off-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/570051/ +Link: https://lore.kernel.org/r/20231201211845.1026967-12-dmitry.baryshkov@linaro.org +Stable-dep-of: aedf02e46eb5 ("drm/msm/dpu: move dpu_encoder's connector assignment to atomic_enable()") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++---- + .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++++--- + .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 15 ++++--------- + .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 ++++-------- + .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 21 ++++--------------- + 5 files changed, 22 insertions(+), 44 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +index e454b80907121..781adb5e2c595 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +@@ -2172,6 +2172,7 @@ static void dpu_encoder_early_unregister(struct drm_encoder *encoder) + } + + static int dpu_encoder_virt_add_phys_encs( ++ struct drm_device *dev, + struct msm_display_info *disp_info, + struct dpu_encoder_virt *dpu_enc, + struct dpu_enc_phys_init_params *params) +@@ -2193,7 +2194,7 @@ static int dpu_encoder_virt_add_phys_encs( + + + if (disp_info->intf_type == INTF_WB) { +- enc = dpu_encoder_phys_wb_init(params); ++ enc = dpu_encoder_phys_wb_init(dev, params); + + if (IS_ERR(enc)) { + DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", +@@ -2204,7 +2205,7 @@ static int dpu_encoder_virt_add_phys_encs( + dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; + ++dpu_enc->num_phys_encs; + } else if (disp_info->is_cmd_mode) { +- enc = dpu_encoder_phys_cmd_init(params); ++ enc = dpu_encoder_phys_cmd_init(dev, params); + + if (IS_ERR(enc)) { + DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", +@@ -2215,7 +2216,7 @@ static int dpu_encoder_virt_add_phys_encs( + dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; + ++dpu_enc->num_phys_encs; + } else { +- enc = dpu_encoder_phys_vid_init(params); ++ enc = dpu_encoder_phys_vid_init(dev, params); + + if (IS_ERR(enc)) { + DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", +@@ -2304,7 +2305,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, + break; + } + +- ret = dpu_encoder_virt_add_phys_encs(disp_info, ++ ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info, + dpu_enc, &phys_params); + if (ret) { + DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +index f91661a698882..99997707b0ee9 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +@@ -281,22 +281,24 @@ struct dpu_encoder_wait_info { + * @p: Pointer to init params structure + * Return: Error code or newly allocated encoder + */ +-struct dpu_encoder_phys *dpu_encoder_phys_vid_init( ++struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, + struct dpu_enc_phys_init_params *p); + + /** + * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder ++ * @dev: Corresponding device for devres management + * @p: Pointer to init params structure + * Return: Error code or newly allocated encoder + */ +-struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( ++struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, + struct dpu_enc_phys_init_params *p); + + /** + * dpu_encoder_phys_wb_init - initialize writeback encoder ++ * @dev: Corresponding device for devres management + * @init: Pointer to init info structure with initialization params + */ +-struct dpu_encoder_phys *dpu_encoder_phys_wb_init( ++struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev, + struct dpu_enc_phys_init_params *p); + + /** +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +index 718421306247f..548be5cf07be8 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +@@ -13,6 +13,8 @@ + #include "dpu_trace.h" + #include "disp/msm_disp_snapshot.h" + ++#include ++ + #define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ + (e) && (e)->base.parent ? \ + (e)->base.parent->base.id : -1, \ +@@ -564,14 +566,6 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) + phys_enc->enable_state = DPU_ENC_DISABLED; + } + +-static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc) +-{ +- struct dpu_encoder_phys_cmd *cmd_enc = +- to_dpu_encoder_phys_cmd(phys_enc); +- +- kfree(cmd_enc); +-} +- + static void dpu_encoder_phys_cmd_prepare_for_kickoff( + struct dpu_encoder_phys *phys_enc) + { +@@ -737,7 +731,6 @@ static void dpu_encoder_phys_cmd_init_ops( + ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; + ops->enable = dpu_encoder_phys_cmd_enable; + ops->disable = dpu_encoder_phys_cmd_disable; +- ops->destroy = dpu_encoder_phys_cmd_destroy; + ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq; + ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done; + ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff; +@@ -752,7 +745,7 @@ static void dpu_encoder_phys_cmd_init_ops( + ops->get_line_count = dpu_encoder_phys_cmd_get_line_count; + } + +-struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( ++struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, + struct dpu_enc_phys_init_params *p) + { + struct dpu_encoder_phys *phys_enc = NULL; +@@ -760,7 +753,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( + + DPU_DEBUG("intf\n"); + +- cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL); ++ cmd_enc = drmm_kzalloc(dev, sizeof(*cmd_enc), GFP_KERNEL); + if (!cmd_enc) { + DPU_ERROR("failed to allocate\n"); + return ERR_PTR(-ENOMEM); +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +index aec3ca4aa0fb7..ab26e21871235 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +@@ -11,6 +11,8 @@ + #include "dpu_trace.h" + #include "disp/msm_disp_snapshot.h" + ++#include ++ + #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ + (e) && (e)->parent ? \ + (e)->parent->base.id : -1, \ +@@ -441,12 +443,6 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) + phys_enc->enable_state = DPU_ENC_ENABLING; + } + +-static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) +-{ +- DPU_DEBUG_VIDENC(phys_enc, "\n"); +- kfree(phys_enc); +-} +- + static int dpu_encoder_phys_vid_wait_for_vblank( + struct dpu_encoder_phys *phys_enc) + { +@@ -684,7 +680,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) + ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; + ops->enable = dpu_encoder_phys_vid_enable; + ops->disable = dpu_encoder_phys_vid_disable; +- ops->destroy = dpu_encoder_phys_vid_destroy; + ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; + ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; + ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank; +@@ -697,7 +692,7 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) + ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count; + } + +-struct dpu_encoder_phys *dpu_encoder_phys_vid_init( ++struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, + struct dpu_enc_phys_init_params *p) + { + struct dpu_encoder_phys *phys_enc = NULL; +@@ -707,7 +702,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( + return ERR_PTR(-EINVAL); + } + +- phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL); ++ phys_enc = drmm_kzalloc(dev, sizeof(*phys_enc), GFP_KERNEL); + if (!phys_enc) { + DPU_ERROR("failed to create encoder due to memory allocation error\n"); + return ERR_PTR(-ENOMEM); +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +index a81a9ee71a86c..0a45c546b03f2 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +@@ -8,6 +8,7 @@ + #include + + #include ++#include + + #include "dpu_encoder_phys.h" + #include "dpu_formats.h" +@@ -546,20 +547,6 @@ static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc) + phys_enc->enable_state = DPU_ENC_DISABLED; + } + +-/** +- * dpu_encoder_phys_wb_destroy - destroy writeback encoder +- * @phys_enc: Pointer to physical encoder +- */ +-static void dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc) +-{ +- if (!phys_enc) +- return; +- +- DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); +- +- kfree(phys_enc); +-} +- + static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc, + struct drm_writeback_job *job) + { +@@ -655,7 +642,6 @@ static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) + ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set; + ops->enable = dpu_encoder_phys_wb_enable; + ops->disable = dpu_encoder_phys_wb_disable; +- ops->destroy = dpu_encoder_phys_wb_destroy; + ops->atomic_check = dpu_encoder_phys_wb_atomic_check; + ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done; + ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff; +@@ -671,9 +657,10 @@ static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) + + /** + * dpu_encoder_phys_wb_init - initialize writeback encoder ++ * @dev: Corresponding device for devres management + * @p: Pointer to init info structure with initialization params + */ +-struct dpu_encoder_phys *dpu_encoder_phys_wb_init( ++struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev, + struct dpu_enc_phys_init_params *p) + { + struct dpu_encoder_phys *phys_enc = NULL; +@@ -686,7 +673,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init( + return ERR_PTR(-EINVAL); + } + +- wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL); ++ wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL); + if (!wb_enc) { + DPU_ERROR("failed to allocate wb phys_enc enc\n"); + return ERR_PTR(-ENOMEM); +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-fix-the-highest_bank_bit-for-sc7180.patch b/queue-6.6/drm-msm-fix-the-highest_bank_bit-for-sc7180.patch new file mode 100644 index 00000000000..b41daf4b2d2 --- /dev/null +++ b/queue-6.6/drm-msm-fix-the-highest_bank_bit-for-sc7180.patch @@ -0,0 +1,46 @@ +From 6afe83781af3e689b1564a937d0be0495828b313 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Aug 2024 16:52:27 -0700 +Subject: drm/msm: fix the highest_bank_bit for sc7180 + +From: Abhinav Kumar + +[ Upstream commit 3e30296b374af33cb4c12ff93df0b1e5b2d0f80b ] + +sc7180 programs the ubwc settings as 0x1e as that would mean a +highest bank bit of 14 which matches what the GPU sets as well. + +However, the highest_bank_bit field of the msm_mdss_data which is +being used to program the SSPP's fetch configuration is programmed +to a highest bank bit of 16 as 0x3 translates to 16 and not 14. + +Fix the highest bank bit field used for the SSPP to match the mdss +and gpu settings. + +Fixes: 6f410b246209 ("drm/msm/mdss: populate missing data") +Reviewed-by: Rob Clark +Tested-by: Stephen Boyd # Trogdor.Lazor +Patchwork: https://patchwork.freedesktop.org/patch/607625/ +Link: https://lore.kernel.org/r/20240808235227.2701479-1-quic_abhinavk@quicinc.com +Signed-off-by: Abhinav Kumar +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/msm_mdss.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index 222b72dc52269..69d10acd8ca74 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -531,7 +531,7 @@ static const struct msm_mdss_data sc7180_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .ubwc_static = 0x1e, +- .highest_bank_bit = 0x3, ++ .highest_bank_bit = 0x1, + .reg_bus_bw = 76800, + }; + +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-mdss-handle-the-reg-bus-icc-path.patch b/queue-6.6/drm-msm-mdss-handle-the-reg-bus-icc-path.patch new file mode 100644 index 00000000000..7363ae72807 --- /dev/null +++ b/queue-6.6/drm-msm-mdss-handle-the-reg-bus-icc-path.patch @@ -0,0 +1,247 @@ +From b5bb798714443ee3536c66097aefbfadde45c621 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Dec 2023 01:42:47 +0300 +Subject: drm/msm/mdss: Handle the reg bus ICC path + +From: Dmitry Baryshkov + +[ Upstream commit a55c8ff252d374acb6f78b979cadc38073ce95e8 ] + +Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's +another path that needs to be handled to ensure MDSS functions properly, +namely the "reg bus", a.k.a the CPU-MDSS interconnect. + +Gating that path may have a variety of effects, from none to otherwise +inexplicable DSI timeouts. + +Provide a way for MDSS driver to vote on this bus. + +A note regarding vote values. Newer platforms have corresponding +bandwidth values in the vendor DT files. For the older platforms there +was a static vote in the mdss_mdp and rotator drivers. I choose to be +conservative here and choose this value as a default. + +Co-developed-by: Konrad Dybcio +Signed-off-by: Konrad Dybcio +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/570164/ +Link: https://lore.kernel.org/r/20231202224247.1282567-5-dmitry.baryshkov@linaro.org +Stable-dep-of: 3e30296b374a ("drm/msm: fix the highest_bank_bit for sc7180") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/msm_mdss.c | 49 +++++++++++++++++++++++++++++++--- + drivers/gpu/drm/msm/msm_mdss.h | 1 + + 2 files changed, 46 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index cce3eb505bf46..222b72dc52269 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -28,6 +28,8 @@ + + #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ + ++#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */ ++ + struct msm_mdss { + struct device *dev; + +@@ -42,6 +44,7 @@ struct msm_mdss { + const struct msm_mdss_data *mdss_data; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; ++ struct icc_path *reg_bus_path; + }; + + static int msm_mdss_parse_data_bus_icc_path(struct device *dev, +@@ -49,6 +52,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + { + struct icc_path *path0; + struct icc_path *path1; ++ struct icc_path *reg_bus_path; + + path0 = devm_of_icc_get(dev, "mdp0-mem"); + if (IS_ERR_OR_NULL(path0)) +@@ -63,6 +67,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + msm_mdss->num_mdp_paths++; + } + ++ reg_bus_path = of_icc_get(dev, "cpu-cfg"); ++ if (!IS_ERR_OR_NULL(reg_bus_path)) ++ msm_mdss->reg_bus_path = reg_bus_path; ++ + return 0; + } + +@@ -236,6 +244,13 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) + */ + msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); + ++ if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) ++ icc_set_bw(msm_mdss->reg_bus_path, 0, ++ msm_mdss->mdss_data->reg_bus_bw); ++ else ++ icc_set_bw(msm_mdss->reg_bus_path, 0, ++ DEFAULT_REG_BW); ++ + ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); + if (ret) { + dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); +@@ -289,6 +304,9 @@ static int msm_mdss_disable(struct msm_mdss *msm_mdss) + clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); + msm_mdss_icc_request_bw(msm_mdss, 0); + ++ if (msm_mdss->reg_bus_path) ++ icc_set_bw(msm_mdss->reg_bus_path, 0, 0); ++ + return 0; + } + +@@ -375,6 +393,8 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 + if (!msm_mdss) + return ERR_PTR(-ENOMEM); + ++ msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev); ++ + msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); + if (IS_ERR(msm_mdss->mmio)) + return ERR_CAST(msm_mdss->mmio); +@@ -465,8 +485,6 @@ static int mdss_probe(struct platform_device *pdev) + if (IS_ERR(mdss)) + return PTR_ERR(mdss); + +- mdss->mdss_data = of_device_get_match_data(&pdev->dev); +- + platform_set_drvdata(pdev, mdss); + + /* +@@ -500,11 +518,13 @@ static const struct msm_mdss_data msm8998_data = { + .ubwc_enc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_1_0, + .highest_bank_bit = 2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data qcm2290_data = { + /* no UBWC */ + .highest_bank_bit = 0x2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sc7180_data = { +@@ -512,6 +532,7 @@ static const struct msm_mdss_data sc7180_data = { + .ubwc_dec_version = UBWC_2_0, + .ubwc_static = 0x1e, + .highest_bank_bit = 0x3, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sc7280_data = { +@@ -521,6 +542,7 @@ static const struct msm_mdss_data sc7280_data = { + .ubwc_static = 1, + .highest_bank_bit = 1, + .macrotile_mode = 1, ++ .reg_bus_bw = 74000, + }; + + static const struct msm_mdss_data sc8180x_data = { +@@ -528,6 +550,7 @@ static const struct msm_mdss_data sc8180x_data = { + .ubwc_dec_version = UBWC_3_0, + .highest_bank_bit = 3, + .macrotile_mode = 1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sc8280xp_data = { +@@ -537,12 +560,14 @@ static const struct msm_mdss_data sc8280xp_data = { + .ubwc_static = 1, + .highest_bank_bit = 2, + .macrotile_mode = 1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sdm845_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm6350_data = { +@@ -551,12 +576,14 @@ static const struct msm_mdss_data sm6350_data = { + .ubwc_swizzle = 6, + .ubwc_static = 0x1e, + .highest_bank_bit = 1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm8150_data = { + .ubwc_enc_version = UBWC_3_0, + .ubwc_dec_version = UBWC_3_0, + .highest_bank_bit = 2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm6115_data = { +@@ -565,6 +592,7 @@ static const struct msm_mdss_data sm6115_data = { + .ubwc_swizzle = 7, + .ubwc_static = 0x11f, + .highest_bank_bit = 0x1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm6125_data = { +@@ -582,6 +610,18 @@ static const struct msm_mdss_data sm8250_data = { + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = 1, ++ .reg_bus_bw = 76800, ++}; ++ ++static const struct msm_mdss_data sm8350_data = { ++ .ubwc_enc_version = UBWC_4_0, ++ .ubwc_dec_version = UBWC_4_0, ++ .ubwc_swizzle = 6, ++ .ubwc_static = 1, ++ /* TODO: highest_bank_bit = 2 for LP_DDR4 */ ++ .highest_bank_bit = 3, ++ .macrotile_mode = 1, ++ .reg_bus_bw = 74000, + }; + + static const struct msm_mdss_data sm8550_data = { +@@ -592,6 +632,7 @@ static const struct msm_mdss_data sm8550_data = { + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = 1, ++ .reg_bus_bw = 57000, + }; + static const struct of_device_id mdss_dt_match[] = { + { .compatible = "qcom,mdss" }, +@@ -608,8 +649,8 @@ static const struct of_device_id mdss_dt_match[] = { + { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, + { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, + { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, +- { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data }, +- { .compatible = "qcom,sm8450-mdss", .data = &sm8250_data }, ++ { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data }, ++ { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data }, + { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, + {} + }; +diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h +index 02bbab42adbc0..3afef4b1786d2 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.h ++++ b/drivers/gpu/drm/msm/msm_mdss.h +@@ -14,6 +14,7 @@ struct msm_mdss_data { + u32 ubwc_static; + u32 highest_bank_bit; + u32 macrotile_mode; ++ u32 reg_bus_bw; + }; + + #define UBWC_1_0 0x10000000 +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-mdss-rename-path-references-to-mdp_path.patch b/queue-6.6/drm-msm-mdss-rename-path-references-to-mdp_path.patch new file mode 100644 index 00000000000..92703312209 --- /dev/null +++ b/queue-6.6/drm-msm-mdss-rename-path-references-to-mdp_path.patch @@ -0,0 +1,75 @@ +From b8f2952587467253544b3f9476bdc5d8b153c2a8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Dec 2023 01:42:45 +0300 +Subject: drm/msm/mdss: Rename path references to mdp_path + +From: Konrad Dybcio + +[ Upstream commit fabaf176322d687b91a4acf1630c0d0a7d097faa ] + +The DPU1 driver needs to handle all MDPn<->DDR paths, as well as +CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are +calculated, but the latter one has static predefines spanning all SoCs. + +In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename +the path-related struct members to include "mdp_". + +Signed-off-by: Konrad Dybcio +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/570163/ +Link: https://lore.kernel.org/r/20231202224247.1282567-3-dmitry.baryshkov@linaro.org +Stable-dep-of: 3e30296b374a ("drm/msm: fix the highest_bank_bit for sc7180") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/msm_mdss.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index 67f225de57d74..cce3eb505bf46 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -40,8 +40,8 @@ struct msm_mdss { + struct irq_domain *domain; + } irq_controller; + const struct msm_mdss_data *mdss_data; +- struct icc_path *path[2]; +- u32 num_paths; ++ struct icc_path *mdp_path[2]; ++ u32 num_mdp_paths; + }; + + static int msm_mdss_parse_data_bus_icc_path(struct device *dev, +@@ -54,13 +54,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + if (IS_ERR_OR_NULL(path0)) + return PTR_ERR_OR_ZERO(path0); + +- msm_mdss->path[0] = path0; +- msm_mdss->num_paths = 1; ++ msm_mdss->mdp_path[0] = path0; ++ msm_mdss->num_mdp_paths = 1; + + path1 = devm_of_icc_get(dev, "mdp1-mem"); + if (!IS_ERR_OR_NULL(path1)) { +- msm_mdss->path[1] = path1; +- msm_mdss->num_paths++; ++ msm_mdss->mdp_path[1] = path1; ++ msm_mdss->num_mdp_paths++; + } + + return 0; +@@ -70,8 +70,8 @@ static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) + { + int i; + +- for (i = 0; i < msm_mdss->num_paths; i++) +- icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); ++ for (i = 0; i < msm_mdss->num_mdp_paths; i++) ++ icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); + } + + static void msm_mdss_irq(struct irq_desc *desc) +-- +2.43.0 + diff --git a/queue-6.6/drm-msm-mdss-switch-mdss-to-use-devm_of_icc_get.patch b/queue-6.6/drm-msm-mdss-switch-mdss-to-use-devm_of_icc_get.patch new file mode 100644 index 00000000000..38a1120112e --- /dev/null +++ b/queue-6.6/drm-msm-mdss-switch-mdss-to-use-devm_of_icc_get.patch @@ -0,0 +1,73 @@ +From 930f7cb5fbb2a4fd28f64f390d11506b944dbfd7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Dec 2023 01:42:44 +0300 +Subject: drm/msm/mdss: switch mdss to use devm_of_icc_get() + +From: Dmitry Baryshkov + +[ Upstream commit ded61d7dc5a0f8cfe7390aba33187c862d09b177 ] + +Stop using hand-written reset function for ICC release, use +devm_of_icc_get() instead. + +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Konrad Dybcio +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/570161/ +Link: https://lore.kernel.org/r/20231202224247.1282567-2-dmitry.baryshkov@linaro.org +Stable-dep-of: 3e30296b374a ("drm/msm: fix the highest_bank_bit for sc7180") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/msm_mdss.c | 16 ++-------------- + 1 file changed, 2 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index 348c66b146834..67f225de57d74 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -50,14 +50,14 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + struct icc_path *path0; + struct icc_path *path1; + +- path0 = of_icc_get(dev, "mdp0-mem"); ++ path0 = devm_of_icc_get(dev, "mdp0-mem"); + if (IS_ERR_OR_NULL(path0)) + return PTR_ERR_OR_ZERO(path0); + + msm_mdss->path[0] = path0; + msm_mdss->num_paths = 1; + +- path1 = of_icc_get(dev, "mdp1-mem"); ++ path1 = devm_of_icc_get(dev, "mdp1-mem"); + if (!IS_ERR_OR_NULL(path1)) { + msm_mdss->path[1] = path1; + msm_mdss->num_paths++; +@@ -66,15 +66,6 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + return 0; + } + +-static void msm_mdss_put_icc_path(void *data) +-{ +- struct msm_mdss *msm_mdss = data; +- int i; +- +- for (i = 0; i < msm_mdss->num_paths; i++) +- icc_put(msm_mdss->path[i]); +-} +- + static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) + { + int i; +@@ -391,9 +382,6 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 + dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); + + ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); +- if (ret) +- return ERR_PTR(ret); +- ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); + if (ret) + return ERR_PTR(ret); + +-- +2.43.0 + diff --git a/queue-6.6/mmc-mmc_test-fix-null-dereference-on-allocation-fail.patch b/queue-6.6/mmc-mmc_test-fix-null-dereference-on-allocation-fail.patch new file mode 100644 index 00000000000..5da6b82f355 --- /dev/null +++ b/queue-6.6/mmc-mmc_test-fix-null-dereference-on-allocation-fail.patch @@ -0,0 +1,55 @@ +From 6f1c1948f8b5e82d861ac0bb1f34c72da10ca05f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Aug 2024 11:44:08 +0300 +Subject: mmc: mmc_test: Fix NULL dereference on allocation failure + +From: Dan Carpenter + +[ Upstream commit a1e627af32ed60713941cbfc8075d44cad07f6dd ] + +If the "test->highmem = alloc_pages()" allocation fails then calling +__free_pages(test->highmem) will result in a NULL dereference. Also +change the error code to -ENOMEM instead of returning success. + +Fixes: 2661081f5ab9 ("mmc_test: highmem tests") +Signed-off-by: Dan Carpenter +Link: https://lore.kernel.org/r/8c90be28-67b4-4b0d-a105-034dc72a0b31@stanley.mountain +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/core/mmc_test.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/mmc/core/mmc_test.c b/drivers/mmc/core/mmc_test.c +index 0f6a563103fd2..d780880ddd14b 100644 +--- a/drivers/mmc/core/mmc_test.c ++++ b/drivers/mmc/core/mmc_test.c +@@ -3104,13 +3104,13 @@ static ssize_t mtf_test_write(struct file *file, const char __user *buf, + test->buffer = kzalloc(BUFFER_SIZE, GFP_KERNEL); + #ifdef CONFIG_HIGHMEM + test->highmem = alloc_pages(GFP_KERNEL | __GFP_HIGHMEM, BUFFER_ORDER); ++ if (!test->highmem) { ++ count = -ENOMEM; ++ goto free_test_buffer; ++ } + #endif + +-#ifdef CONFIG_HIGHMEM +- if (test->buffer && test->highmem) { +-#else + if (test->buffer) { +-#endif + mutex_lock(&mmc_test_lock); + mmc_test_run(test, testcase); + mutex_unlock(&mmc_test_lock); +@@ -3118,6 +3118,7 @@ static ssize_t mtf_test_write(struct file *file, const char __user *buf, + + #ifdef CONFIG_HIGHMEM + __free_pages(test->highmem, BUFFER_ORDER); ++free_test_buffer: + #endif + kfree(test->buffer); + kfree(test); +-- +2.43.0 + diff --git a/queue-6.6/series b/queue-6.6/series index 31f173b8127..304f9deba4f 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -274,3 +274,20 @@ octeontx2-af-fix-cpt-af-register-offset-calculation.patch net-xilinx-axienet-always-disable-promiscuous-mode.patch net-xilinx-axienet-fix-dangling-multicast-addresses.patch net-ovs-fix-ovs_drop_reasons-error.patch +drm-msm-dpu-don-t-play-tricks-with-debug-macros.patch +drm-msm-dp-fix-the-max-supported-bpp-logic.patch +drm-msm-dpu-use-drmm-managed-allocation-for-dpu_enco.patch +drm-msm-dpu-drop-msm_enc_vblank-support.patch +drm-msm-dpu-split-dpu_encoder_wait_for_event-into-tw.patch +drm-msm-dpu-capture-snapshot-on-the-first-commit_don.patch +drm-msm-dpu-move-dpu_encoder-s-connector-assignment-.patch +drm-msm-dp-reset-the-link-phy-params-before-link-tra.patch +drm-msm-dpu-cleanup-fb-if-dpu_format_populate_layout.patch +drm-msm-dpu-try-multirect-based-on-mdp-clock-limits.patch +drm-msm-dpu-take-plane-rotation-into-account-for-wid.patch +drm-msm-mdss-switch-mdss-to-use-devm_of_icc_get.patch +drm-msm-mdss-rename-path-references-to-mdp_path.patch +drm-msm-mdss-handle-the-reg-bus-icc-path.patch +drm-msm-fix-the-highest_bank_bit-for-sc7180.patch +mmc-mmc_test-fix-null-dereference-on-allocation-fail.patch +smb-client-ignore-unhandled-reparse-tags.patch diff --git a/queue-6.6/smb-client-ignore-unhandled-reparse-tags.patch b/queue-6.6/smb-client-ignore-unhandled-reparse-tags.patch new file mode 100644 index 00000000000..349ed5871ab --- /dev/null +++ b/queue-6.6/smb-client-ignore-unhandled-reparse-tags.patch @@ -0,0 +1,57 @@ +From c2517227cf624fc85f8e45fba1a81fdb9b0460c3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Aug 2024 00:45:03 -0300 +Subject: smb: client: ignore unhandled reparse tags + +From: Paulo Alcantara + +[ Upstream commit ec686804117a0421cf31d54427768aaf93aa0069 ] + +Just ignore reparse points that the client can't parse rather than +bailing out and not opening the file or directory. + +Reported-by: Marc <1marc1@gmail.com> +Closes: https://lore.kernel.org/r/CAMHwNVv-B+Q6wa0FEXrAuzdchzcJRsPKDDRrNaYZJd6X-+iJzw@mail.gmail.com +Fixes: 539aad7f14da ("smb: client: introduce ->parse_reparse_point()") +Tested-by: Anthony Nandaa (Microsoft) +Signed-off-by: Paulo Alcantara (Red Hat) +Signed-off-by: Steve French +Signed-off-by: Sasha Levin +--- + fs/smb/client/reparse.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/fs/smb/client/reparse.c b/fs/smb/client/reparse.c +index 689d8a506d459..48c27581ec511 100644 +--- a/fs/smb/client/reparse.c ++++ b/fs/smb/client/reparse.c +@@ -378,6 +378,8 @@ int parse_reparse_point(struct reparse_data_buffer *buf, + u32 plen, struct cifs_sb_info *cifs_sb, + bool unicode, struct cifs_open_info_data *data) + { ++ struct cifs_tcon *tcon = cifs_sb_master_tcon(cifs_sb); ++ + data->reparse.buf = buf; + + /* See MS-FSCC 2.1.2 */ +@@ -394,12 +396,13 @@ int parse_reparse_point(struct reparse_data_buffer *buf, + case IO_REPARSE_TAG_LX_FIFO: + case IO_REPARSE_TAG_LX_CHR: + case IO_REPARSE_TAG_LX_BLK: +- return 0; ++ break; + default: +- cifs_dbg(VFS, "%s: unhandled reparse tag: 0x%08x\n", +- __func__, le32_to_cpu(buf->ReparseTag)); +- return -EOPNOTSUPP; ++ cifs_tcon_dbg(VFS | ONCE, "unhandled reparse tag: 0x%08x\n", ++ le32_to_cpu(buf->ReparseTag)); ++ break; + } ++ return 0; + } + + int smb2_parse_reparse_point(struct cifs_sb_info *cifs_sb, +-- +2.43.0 +