From: Robert Marko Date: Thu, 2 Jul 2026 11:09:27 +0000 (+0200) Subject: microchip: update TAS patch to pending one X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=b994fb029a90a367ba413f9250d06c677c6708cf;p=thirdparty%2Fopenwrt.git microchip: update TAS patch to pending one Update the TAS patch to the one sent upstream, it adds SparX-5 registers. Signed-off-by: Robert Marko --- diff --git a/target/linux/microchipsw/patches-6.18/131-net-sparx5-configure-TAS-port-link-speed.patch b/target/linux/microchipsw/patches-6.18/131-net-sparx5-configure-TAS-port-link-speed.patch index 713e0474d30..4dc07b4fc48 100644 --- a/target/linux/microchipsw/patches-6.18/131-net-sparx5-configure-TAS-port-link-speed.patch +++ b/target/linux/microchipsw/patches-6.18/131-net-sparx5-configure-TAS-port-link-speed.patch @@ -1,9 +1,9 @@ -From 074d87ae70e2b549001c31f87f2a585225f2e99d Mon Sep 17 00:00:00 2001 +From 2ad75da9a7b7fa1fed92624685c0e9c25fcad719 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 1 Jul 2026 15:37:32 +0200 -Subject: [PATCH] net: sparx5: configure TAS port link speed +Subject: [RFC net-next] net: sparx5: configure TAS port link speed -On the TSN and RED variants of SparX-5 and LAN969x TAS (Time-Aware Shaper) +On the TSN and RED variants of LAN969x and SparX-5i TAS (Time-Aware Shaper) is present in the silicon. Currently, the driver does not use configure it at all, which means that @@ -29,8 +29,9 @@ Signed-off-by: Robert Marko .../ethernet/microchip/sparx5/sparx5_port.c | 4 ++ .../ethernet/microchip/sparx5/sparx5_qos.c | 49 +++++++++++++++++++ .../ethernet/microchip/sparx5/sparx5_qos.h | 1 + + .../ethernet/microchip/sparx5/sparx5_regs.c | 3 ++ .../ethernet/microchip/sparx5/sparx5_regs.h | 3 ++ - 6 files changed, 72 insertions(+) + 7 files changed, 75 insertions(+) --- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_regs.c +++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_regs.c @@ -171,6 +172,32 @@ Signed-off-by: Robert Marko /* Multi-Queue Priority */ int sparx5_tc_mqprio_add(struct net_device *ndev, u8 num_tc); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c +@@ -95,6 +95,7 @@ const unsigned int sparx5_gaddr[GADDR_LA + [GA_HSCH_SYSTEM] = 184000, + [GA_HSCH_MMGT] = 162368, + [GA_HSCH_TAS_CONFIG] = 162384, ++ [GA_HSCH_TAS_PROFILE_CFG] = 188416, + [GA_PTP_PTP_CFG] = 320, + [GA_PTP_PTP_TOD_DOMAINS] = 336, + [GA_PTP_PHASE_DETECTOR_CTRL] = 420, +@@ -129,6 +130,7 @@ const unsigned int sparx5_gcnt[GCNT_LAST + [GC_GCB_SIO_CTRL] = 3, + [GC_HSCH_HSCH_CFG] = 5040, + [GC_HSCH_HSCH_DWRR] = 72, ++ [GC_HSCH_TAS_PROFILE_CFG] = 100, + [GC_PTP_PTP_PINS] = 5, + [GC_PTP_PHASE_DETECTOR_CTRL] = 5, + [GC_REW_PORT] = 70, +@@ -144,6 +146,7 @@ const unsigned int sparx5_gsize[GSIZE_LA + [GW_FDMA_FDMA] = 428, + [GW_GCB_CHIP_REGS] = 424, + [GW_HSCH_TAS_CONFIG] = 12, ++ [GW_HSCH_TAS_PROFILE_CFG] = 64, + [GW_PTP_PHASE_DETECTOR_CTRL] = 8, + [GW_QSYS_PAUSE_CFG] = 1128, + }; --- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h @@ -104,6 +104,7 @@ enum sparx5_gaddr_enum {