From: Jonas Jelonek Date: Wed, 18 Mar 2026 21:02:55 +0000 (+0100) Subject: realtek: pcs: rtl930x: move EEE to USXGMII configuration X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=bab2bcd9d8b2d9cb8d38317dd70872b68bbdcb5e;p=thirdparty%2Fopenwrt.git realtek: pcs: rtl930x: move EEE to USXGMII configuration The patch/config sequences for USXGMII modes contain a register write which is explicitly labelled as "enable eee". To clean the sequences and reduce duplication, move this specific write to the USXGMII configuration function. While at it, demystify this register write. From [1] we can see that only a single bit needs to be set for controlling EEE instead of the whole register. From testing it was seen that the register has a default value of 0x445C after reset. Thus, there is no other operation hidden in this write and we're safe to reduce it to setting just the EEE enable bit. [1] https://github.com/plappermaul/realtek-doc/blob/82af3a36b7f65dbe2158fef3a9b71e7aab94315e/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22582 Signed-off-by: Robert Marko --- diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index b1be0581c37..7bcce048e6a 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -2887,8 +2887,6 @@ static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_usxgmii_sx_even[] = {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x66E1}, - /*enable eee*/ - {0x06, 0x03, 0xc45c}, }; static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_usxgmii_sx_odd[] = @@ -2905,8 +2903,6 @@ static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_usxgmii_sx_odd[] = {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},{0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},{0x2D, 0x14, 0x1808}, - /*enable eee*/ - {0x06, 0x03, 0xc45c}, }; static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_5g_qsgmii[] = @@ -2950,6 +2946,8 @@ static void rtpcs_930x_sds_usxgmii_config(struct rtpcs_serdes *sds, bool nway_en rtpcs_sds_write_bits(sds, 0x6, 0x18, 15, 8, all_am_markers); /* CFG_AM3_M2 */ rtpcs_sds_write_bits(sds, 0x6, 0xe, 10, 10, an_table); rtpcs_sds_write_bits(sds, 0x6, 0x1d, 11, 10, sync_bit); + + rtpcs_sds_write_bits(sds, 0x06, 0x03, 15, 15, 0x1); /* FP_TGR3_CFG_EEE_EN */ } static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode)