From: Greg Kroah-Hartman Date: Sun, 27 Aug 2023 07:02:14 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v6.1.49~36 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=c10e82583fd8bbe77cfa4b9ae154bf696b130868;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: drm-display-dp-fix-the-dp-dsc-receiver-cap-size.patch x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch --- diff --git a/queue-5.4/drm-display-dp-fix-the-dp-dsc-receiver-cap-size.patch b/queue-5.4/drm-display-dp-fix-the-dp-dsc-receiver-cap-size.patch new file mode 100644 index 00000000000..19ecca580d0 --- /dev/null +++ b/queue-5.4/drm-display-dp-fix-the-dp-dsc-receiver-cap-size.patch @@ -0,0 +1,37 @@ +From 5ad1ab30ac0809d2963ddcf39ac34317a24a2f17 Mon Sep 17 00:00:00 2001 +From: Ankit Nautiyal +Date: Fri, 18 Aug 2023 10:14:36 +0530 +Subject: drm/display/dp: Fix the DP DSC Receiver cap size + +From: Ankit Nautiyal + +commit 5ad1ab30ac0809d2963ddcf39ac34317a24a2f17 upstream. + +DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh. +Fix the DSC RECEIVER CAP SIZE accordingly. + +Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT") +Cc: Anusha Srivatsa +Cc: Manasi Navare +Cc: # v5.0+ + +Signed-off-by: Ankit Nautiyal +Reviewed-by: Stanislav Lisovskiy +Signed-off-by: Jani Nikula +Link: https://patchwork.freedesktop.org/patch/msgid/20230818044436.177806-1-ankit.k.nautiyal@intel.com +Signed-off-by: Greg Kroah-Hartman +--- + include/drm/drm_dp_helper.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/include/drm/drm_dp_helper.h ++++ b/include/drm/drm_dp_helper.h +@@ -1052,7 +1052,7 @@ u8 drm_dp_get_adjust_request_pre_emphasi + + #define DP_BRANCH_OUI_HEADER_SIZE 0xc + #define DP_RECEIVER_CAP_SIZE 0xf +-#define DP_DSC_RECEIVER_CAP_SIZE 0xf ++#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */ + #define EDP_PSR_RECEIVER_CAP_SIZE 2 + #define EDP_DISPLAY_CTL_CAP_SIZE 3 + diff --git a/queue-5.4/series b/queue-5.4/series index 28aa8cc7e4a..49ca61ddf6f 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -143,3 +143,5 @@ lib-clz_ctz.c-fix-__clzdi2-and-__ctzdi2-for-32-bit-kernels.patch radix-tree-remove-unused-variable.patch media-vcodec-fix-potential-array-out-of-bounds-in-encoder-queue_setup.patch pci-acpiphp-use-pci_assign_unassigned_bridge_resources-only-for-non-root-bus.patch +drm-display-dp-fix-the-dp-dsc-receiver-cap-size.patch +x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch diff --git a/queue-5.4/x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch b/queue-5.4/x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch new file mode 100644 index 00000000000..c53b3ca74d5 --- /dev/null +++ b/queue-5.4/x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch @@ -0,0 +1,62 @@ +From 2c66ca3949dc701da7f4c9407f2140ae425683a5 Mon Sep 17 00:00:00 2001 +From: Feng Tang +Date: Wed, 23 Aug 2023 14:57:47 +0800 +Subject: x86/fpu: Set X86_FEATURE_OSXSAVE feature after enabling OSXSAVE in CR4 + +From: Feng Tang + +commit 2c66ca3949dc701da7f4c9407f2140ae425683a5 upstream. + +0-Day found a 34.6% regression in stress-ng's 'af-alg' test case, and +bisected it to commit b81fac906a8f ("x86/fpu: Move FPU initialization into +arch_cpu_finalize_init()"), which optimizes the FPU init order, and moves +the CR4_OSXSAVE enabling into a later place: + + arch_cpu_finalize_init + identify_boot_cpu + identify_cpu + generic_identify + get_cpu_cap --> setup cpu capability + ... + fpu__init_cpu + fpu__init_cpu_xstate + cr4_set_bits(X86_CR4_OSXSAVE); + +As the FPU is not yet initialized the CPU capability setup fails to set +X86_FEATURE_OSXSAVE. Many security module like 'camellia_aesni_avx_x86_64' +depend on this feature and therefore fail to load, causing the regression. + +Cure this by setting X86_FEATURE_OSXSAVE feature right after OSXSAVE +enabling. + +[ tglx: Moved it into the actual BSP FPU initialization code and added a comment ] + +Fixes: b81fac906a8f ("x86/fpu: Move FPU initialization into arch_cpu_finalize_init()") +Reported-by: kernel test robot +Signed-off-by: Feng Tang +Signed-off-by: Thomas Gleixner +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/lkml/202307192135.203ac24e-oliver.sang@intel.com +Link: https://lore.kernel.org/lkml/20230823065747.92257-1-feng.tang@intel.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/fpu/xstate.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/x86/kernel/fpu/xstate.c ++++ b/arch/x86/kernel/fpu/xstate.c +@@ -805,6 +805,14 @@ void __init fpu__init_system_xstate(void + fpu__init_prepare_fx_sw_frame(); + setup_init_fpu_buf(); + setup_xstate_comp(); ++ ++ /* ++ * CPU capabilities initialization runs before FPU init. So ++ * X86_FEATURE_OSXSAVE is not set. Now that XSAVE is completely ++ * functional, set the feature bit so depending code works. ++ */ ++ setup_force_cpu_cap(X86_FEATURE_OSXSAVE); ++ + print_xstate_offset_size(); + + pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n",