From: Greg Kroah-Hartman Date: Tue, 10 Jan 2023 17:31:05 +0000 (+0100) Subject: 5.15-stable patches X-Git-Tag: v5.15.87~3 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=c2bf1cc362d4d1f2a74e803900cf345d7d64a1d5;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch --- diff --git a/queue-5.15/drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch b/queue-5.15/drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch new file mode 100644 index 00000000000..694998cf8cc --- /dev/null +++ b/queue-5.15/drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch @@ -0,0 +1,45 @@ +From b389286d0234e1edbaf62ed8bc0892a568c33662 Mon Sep 17 00:00:00 2001 +From: Jocelyn Falempe +Date: Thu, 13 Oct 2022 15:28:10 +0200 +Subject: drm/mgag200: Fix PLL setup for G200_SE_A rev >=4 + +From: Jocelyn Falempe + +commit b389286d0234e1edbaf62ed8bc0892a568c33662 upstream. + +For G200_SE_A, PLL M setting is wrong, which leads to blank screen, +or "signal out of range" on VGA display. +previous code had "m |= 0x80" which was changed to +m |= ((pixpllcn & BIT(8)) >> 1); + +Tested on G200_SE_A rev 42 + +This line of code was moved to another file with +commit 877507bb954e ("drm/mgag200: Provide per-device callbacks for +PIXPLLC") but can be easily backported before this commit. + +v2: * put BIT(7) First to respect MSB-to-LSB (Thomas) + * Add a comment to explain that this bit must be set (Thomas) + +Fixes: 2dd040946ecf ("drm/mgag200: Store values (not bits) in struct mgag200_pll_values") +Cc: stable@vger.kernel.org +Signed-off-by: Jocelyn Falempe +Reviewed-by: Thomas Zimmermann +Link: https://patchwork.freedesktop.org/patch/msgid/20221013132810.521945-1-jfalempe@redhat.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/mgag200/mgag200_pll.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/mgag200/mgag200_pll.c ++++ b/drivers/gpu/drm/mgag200/mgag200_pll.c +@@ -268,7 +268,8 @@ static void mgag200_pixpll_update_g200se + pixpllcp = pixpllc->p - 1; + pixpllcs = pixpllc->s; + +- xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1); ++ // For G200SE A, BIT(7) should be set unconditionally. ++ xpixpllcm = BIT(7) | pixpllcm; + xpixpllcn = pixpllcn; + xpixpllcp = (pixpllcs << 3) | pixpllcp; + diff --git a/queue-5.15/series b/queue-5.15/series index 4d6e16e9c35..d220e82a1fd 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -287,3 +287,4 @@ net-hns3-fix-return-value-check-bug-of-rx-copybreak.patch mbcache-avoid-nesting-of-cache-c_list_lock-under-bit-locks.patch efi-random-combine-bootloader-provided-rng-seed-with-rng-protocol-output.patch io_uring-fix-unsigned-res-comparison-with-zero-in-io_fixup_rw_res.patch +drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch