From: Sasha Levin Date: Fri, 9 Sep 2022 02:31:40 +0000 (-0400) Subject: Fixes for 4.14 X-Git-Tag: v5.19.9~71 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=c4af1d9ac5c2b521ae11cef17d8148440a9a859b;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 4.14 Signed-off-by: Sasha Levin --- diff --git a/queue-4.14/arm64-signal-raise-limit-on-stack-frames.patch b/queue-4.14/arm64-signal-raise-limit-on-stack-frames.patch new file mode 100644 index 00000000000..27292f48095 --- /dev/null +++ b/queue-4.14/arm64-signal-raise-limit-on-stack-frames.patch @@ -0,0 +1,44 @@ +From fc7ae800af5800119a26fcd3cc389093e8201bd6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 17 Aug 2022 19:23:21 +0100 +Subject: arm64/signal: Raise limit on stack frames + +From: Mark Brown + +[ Upstream commit 7ddcaf78e93c9282b4d92184f511b4d5bee75355 ] + +The signal code has a limit of 64K on the size of a stack frame that it +will generate, if this limit is exceeded then a process will be killed if +it receives a signal. Unfortunately with the advent of SME this limit is +too small - the maximum possible size of the ZA register alone is 64K. This +is not an issue for practical systems at present but is easily seen using +virtual platforms. + +Raise the limit to 256K, this is substantially more than could be used by +any current architecture extension. + +Signed-off-by: Mark Brown +Acked-by: Catalin Marinas +Link: https://lore.kernel.org/r/20220817182324.638214-2-broonie@kernel.org +Signed-off-by: Will Deacon +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/signal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c +index 43442b3a463f5..1b3973de417ec 100644 +--- a/arch/arm64/kernel/signal.c ++++ b/arch/arm64/kernel/signal.c +@@ -97,7 +97,7 @@ static size_t sigframe_size(struct rt_sigframe_user_layout const *user) + * not taken into account. This limit is not a guarantee and is + * NOT ABI. + */ +-#define SIGFRAME_MAXSZ SZ_64K ++#define SIGFRAME_MAXSZ SZ_256K + + static int __sigframe_alloc(struct rt_sigframe_user_layout *user, + unsigned long *offset, size_t size, bool extend) +-- +2.35.1 + diff --git a/queue-4.14/drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch b/queue-4.14/drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch new file mode 100644 index 00000000000..a8f5c5d4a52 --- /dev/null +++ b/queue-4.14/drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch @@ -0,0 +1,36 @@ +From e2af8b7e4bce4609953bcf6e9584c37a03bb83ca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 18 Aug 2022 10:47:09 +0800 +Subject: drm/amdgpu: Check num_gfx_rings for gfx v9_0 rb setup. + +From: Candice Li + +[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ] + +No need to set up rb when no gfx rings. + +Signed-off-by: Candice Li +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 53186c5e1066b..bb0d32b4be74d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1514,7 +1514,8 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) + + gfx_v9_0_tiling_mode_table_init(adev); + +- gfx_v9_0_setup_rb(adev); ++ if (adev->gfx.num_gfx_rings) ++ gfx_v9_0_setup_rb(adev); + gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); + + /* XXX SH_MEM regs */ +-- +2.35.1 + diff --git a/queue-4.14/drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch b/queue-4.14/drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch new file mode 100644 index 00000000000..d4d1c81675a --- /dev/null +++ b/queue-4.14/drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch @@ -0,0 +1,78 @@ +From b9215d983b8ffdde97e0db07358ac2d07e9c3e08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 11 Aug 2022 15:25:40 +0800 +Subject: drm/radeon: add a force flush to delay work when radeon +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Zhenneng Li + +[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ] + +Although radeon card fence and wait for gpu to finish processing current batch rings, +there is still a corner case that radeon lockup work queue may not be fully flushed, +and meanwhile the radeon_suspend_kms() function has called pci_set_power_state() to +put device in D3hot state. +Per PCI spec rev 4.0 on 5.3.1.4.1 D3hot State. +> Configuration and Message requests are the only TLPs accepted by a Function in +> the D3hot state. All other received Requests must be handled as Unsupported Requests, +> and all received Completions may optionally be handled as Unexpected Completions. +This issue will happen in following logs: +Unable to handle kernel paging request at virtual address 00008800e0008010 +CPU 0 kworker/0:3(131): Oops 0 +pc = [] ra = [] ps = 0000 Tainted: G W +pc is at si_gpu_check_soft_reset+0x3c/0x240 +ra is at si_dma_is_lockup+0x34/0xd0 +v0 = 0000000000000000 t0 = fff08800e0008010 t1 = 0000000000010000 +t2 = 0000000000008010 t3 = fff00007e3c00000 t4 = fff00007e3c00258 +t5 = 000000000000ffff t6 = 0000000000000001 t7 = fff00007ef078000 +s0 = fff00007e3c016e8 s1 = fff00007e3c00000 s2 = fff00007e3c00018 +s3 = fff00007e3c00000 s4 = fff00007fff59d80 s5 = 0000000000000000 +s6 = fff00007ef07bd98 +a0 = fff00007e3c00000 a1 = fff00007e3c016e8 a2 = 0000000000000008 +a3 = 0000000000000001 a4 = 8f5c28f5c28f5c29 a5 = ffffffff810f4338 +t8 = 0000000000000275 t9 = ffffffff809b66f8 t10 = ff6769c5d964b800 +t11= 000000000000b886 pv = ffffffff811bea20 at = 0000000000000000 +gp = ffffffff81d89690 sp = 00000000aa814126 +Disabling lock debugging due to kernel taint +Trace: +[] si_dma_is_lockup+0x34/0xd0 +[] radeon_fence_check_lockup+0xd0/0x290 +[] process_one_work+0x280/0x550 +[] worker_thread+0x70/0x7c0 +[] worker_thread+0x130/0x7c0 +[] kthread+0x200/0x210 +[] worker_thread+0x0/0x7c0 +[] kthread+0x14c/0x210 +[] ret_from_kernel_thread+0x18/0x20 +[] kthread+0x0/0x210 + Code: ad3e0008 43f0074a ad7e0018 ad9e0020 8c3001e8 40230101 + <88210000> 4821ed21 +So force lockup work queue flush to fix this problem. + +Acked-by: Christian König +Signed-off-by: Zhenneng Li +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/radeon_device.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c +index 58488eac84627..906547b229a9a 100644 +--- a/drivers/gpu/drm/radeon/radeon_device.c ++++ b/drivers/gpu/drm/radeon/radeon_device.c +@@ -1655,6 +1655,9 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, + if (r) { + /* delay GPU reset to resume */ + radeon_fence_driver_force_completion(rdev, i); ++ } else { ++ /* finish executing delayed work */ ++ flush_delayed_work(&rdev->fence_drv[i].lockup_work); + } + } + +-- +2.35.1 + diff --git a/queue-4.14/fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch b/queue-4.14/fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch new file mode 100644 index 00000000000..d5ed3ee22fe --- /dev/null +++ b/queue-4.14/fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch @@ -0,0 +1,34 @@ +From 993bf24f3fc22d43f67dd24924ee28ddaeec91b3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 16:57:52 +0800 +Subject: fbdev: chipsfb: Add missing pci_disable_device() in + chipsfb_pci_init() + +From: Yang Yingliang + +[ Upstream commit 07c55c9803dea748d17a054000cbf1913ce06399 ] + +Add missing pci_disable_device() in error path in chipsfb_pci_init(). + +Signed-off-by: Yang Yingliang +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + drivers/video/fbdev/chipsfb.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/video/fbdev/chipsfb.c b/drivers/video/fbdev/chipsfb.c +index 413b465e69d8e..7ca149ab86d20 100644 +--- a/drivers/video/fbdev/chipsfb.c ++++ b/drivers/video/fbdev/chipsfb.c +@@ -432,6 +432,7 @@ static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent) + err_release_fb: + framebuffer_release(p); + err_disable: ++ pci_disable_device(dp); + err_out: + return rc; + } +-- +2.35.1 + diff --git a/queue-4.14/parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch b/queue-4.14/parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch new file mode 100644 index 00000000000..c4581d37444 --- /dev/null +++ b/queue-4.14/parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch @@ -0,0 +1,83 @@ +From b80638ef4b566e43b1a31825fcb01ef163ac1788 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 21 Aug 2022 14:49:58 +0200 +Subject: parisc: Add runtime check to prevent PA2.0 kernels on PA1.x machines + +From: Helge Deller + +[ Upstream commit 591d2108f3abc4db9f9073cae37cf3591fd250d6 ] + +If a 32-bit kernel was compiled for PA2.0 CPUs, it won't be able to run +on machines with PA1.x CPUs. Add a check and bail out early if a PA1.x +machine is detected. + +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + arch/parisc/kernel/head.S | 43 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S +index 9b99eb0712ad1..2f570a5205866 100644 +--- a/arch/parisc/kernel/head.S ++++ b/arch/parisc/kernel/head.S +@@ -22,7 +22,7 @@ + #include + #include + +- .level PA_ASM_LEVEL ++ .level 1.1 + + __INITDATA + ENTRY(boot_args) +@@ -69,6 +69,47 @@ $bss_loop: + stw,ma %arg2,4(%r1) + stw,ma %arg3,4(%r1) + ++#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20) ++ /* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU ++ * and halt kernel if we detect a PA1.x CPU. */ ++ ldi 32,%r10 ++ mtctl %r10,%cr11 ++ .level 2.0 ++ mfctl,w %cr11,%r10 ++ .level 1.1 ++ comib,<>,n 0,%r10,$cpu_ok ++ ++ load32 PA(msg1),%arg0 ++ ldi msg1_end-msg1,%arg1 ++$iodc_panic: ++ copy %arg0, %r10 ++ copy %arg1, %r11 ++ load32 PA(init_stack),%sp ++#define MEM_CONS 0x3A0 ++ ldw MEM_CONS+32(%r0),%arg0 // HPA ++ ldi ENTRY_IO_COUT,%arg1 ++ ldw MEM_CONS+36(%r0),%arg2 // SPA ++ ldw MEM_CONS+8(%r0),%arg3 // layers ++ load32 PA(__bss_start),%r1 ++ stw %r1,-52(%sp) // arg4 ++ stw %r0,-56(%sp) // arg5 ++ stw %r10,-60(%sp) // arg6 = ptr to text ++ stw %r11,-64(%sp) // arg7 = len ++ stw %r0,-68(%sp) // arg8 ++ load32 PA(.iodc_panic_ret), %rp ++ ldw MEM_CONS+40(%r0),%r1 // ENTRY_IODC ++ bv,n (%r1) ++.iodc_panic_ret: ++ b . /* wait endless with ... */ ++ or %r10,%r10,%r10 /* qemu idle sleep */ ++msg1: .ascii "Can't boot kernel which was built for PA8x00 CPUs on this machine.\r\n" ++msg1_end: ++ ++$cpu_ok: ++#endif ++ ++ .level PA_ASM_LEVEL ++ + /* Initialize startup VM. Just map first 16/32 MB of memory */ + load32 PA(swapper_pg_dir),%r4 + mtctl %r4,%cr24 /* Initialize kernel root pointer */ +-- +2.35.1 + diff --git a/queue-4.14/parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch b/queue-4.14/parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch new file mode 100644 index 00000000000..8fda56b2a31 --- /dev/null +++ b/queue-4.14/parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch @@ -0,0 +1,58 @@ +From 6624169fc5668d2b7852c0ff9c8e565259d20950 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 12:15:10 +0800 +Subject: parisc: ccio-dma: Handle kmalloc failure in ccio_init_resources() + +From: Li Qiong + +[ Upstream commit d46c742f827fa2326ab1f4faa1cccadb56912341 ] + +As the possible failure of the kmalloc(), it should be better +to fix this error path, check and return '-ENOMEM' error code. + +Signed-off-by: Li Qiong +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + drivers/parisc/ccio-dma.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c +index 224a364097672..cc23b30337c16 100644 +--- a/drivers/parisc/ccio-dma.c ++++ b/drivers/parisc/ccio-dma.c +@@ -1416,15 +1416,17 @@ ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) + } + } + +-static void __init ccio_init_resources(struct ioc *ioc) ++static int __init ccio_init_resources(struct ioc *ioc) + { + struct resource *res = ioc->mmio_region; + char *name = kmalloc(14, GFP_KERNEL); +- ++ if (unlikely(!name)) ++ return -ENOMEM; + snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); + + ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); + ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); ++ return 0; + } + + static int new_ioc_area(struct resource *res, unsigned long size, +@@ -1578,7 +1580,10 @@ static int __init ccio_probe(struct parisc_device *dev) + return -ENOMEM; + } + ccio_ioc_init(ioc); +- ccio_init_resources(ioc); ++ if (ccio_init_resources(ioc)) { ++ kfree(ioc); ++ return -ENOMEM; ++ } + hppa_dma_ops = &ccio_ops; + dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL); + +-- +2.35.1 + diff --git a/queue-4.14/series b/queue-4.14/series index a5360722192..01415a40d33 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -35,3 +35,9 @@ efi-capsule-loader-fix-use-after-free-in-efi_capsule_write.patch wifi-iwlegacy-4965-corrected-fix-for-potential-off-by-one-overflow-in-il4965_rs_fill_link_cmd.patch fs-only-do-a-memory-barrier-for-the-first-set_buffer_uptodate.patch revert-mm-kmemleak-take-a-full-lowmem-check-in-kmemleak_-_phys.patch +drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch +drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch +parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch +parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch +arm64-signal-raise-limit-on-stack-frames.patch +fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch