From: Greg Kroah-Hartman Date: Thu, 27 Oct 2022 10:16:05 +0000 (+0200) Subject: 5.10-stable patches X-Git-Tag: v5.10.151~23 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=c5b171238405cb860f6115d01b4309e044ed388c;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: arm64-dts-qcom-sc7180-trogdor-fixup-modem-memory-region.patch arm64-topology-move-store_cpu_topology-to-shared-code.patch riscv-topology-fix-default-topology-reporting.patch --- diff --git a/queue-5.10/arm64-dts-qcom-sc7180-trogdor-fixup-modem-memory-region.patch b/queue-5.10/arm64-dts-qcom-sc7180-trogdor-fixup-modem-memory-region.patch new file mode 100644 index 00000000000..e25d9a763a6 --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-sc7180-trogdor-fixup-modem-memory-region.patch @@ -0,0 +1,49 @@ +From ef9a5d188d663753e73a3c8e8910ceab8e9305c4 Mon Sep 17 00:00:00 2001 +From: Sibi Sankar +Date: Thu, 15 Oct 2020 23:57:56 +0530 +Subject: arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region + +From: Sibi Sankar + +commit ef9a5d188d663753e73a3c8e8910ceab8e9305c4 upstream. + +The modem firmware memory requirements vary between 32M/140M on +no-lte/lte skus respectively, so fixup the modem memory region +to reflect the requirements. + +Reviewed-by: Evan Green +Signed-off-by: Sibi Sankar +Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org +Signed-off-by: Bjorn Andersson +Acked-by: Alex Elder +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 ++++ + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi +@@ -9,6 +9,10 @@ + label = "proximity-wifi-lte"; + }; + ++&mpss_mem { ++ reg = <0x0 0x86000000 0x0 0x8c00000>; ++}; ++ + &remoteproc_mpss { + firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn", + "qcom/sc7180-trogdor/modem/qdsp6sw.mbn"; +--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +@@ -39,7 +39,7 @@ + }; + + mpss_mem: memory@86000000 { +- reg = <0x0 0x86000000 0x0 0x8c00000>; ++ reg = <0x0 0x86000000 0x0 0x2000000>; + no-map; + }; + diff --git a/queue-5.10/arm64-topology-move-store_cpu_topology-to-shared-code.patch b/queue-5.10/arm64-topology-move-store_cpu_topology-to-shared-code.patch new file mode 100644 index 00000000000..8b2020a49af --- /dev/null +++ b/queue-5.10/arm64-topology-move-store_cpu_topology-to-shared-code.patch @@ -0,0 +1,109 @@ +From foo@baz Thu Oct 27 12:15:29 PM CEST 2022 +From: Conor Dooley +Date: Wed, 19 Oct 2022 13:53:02 +0100 +Subject: arm64: topology: move store_cpu_topology() to shared code +To: +Cc: , , , , , , , , , , , Atish Patra +Message-ID: <20221019125303.2845522-1-conor.dooley@microchip.com> + +From: Conor Dooley + +commit 456797da792fa7cbf6698febf275fe9b36691f78 upstream. + +arm64's method of defining a default cpu topology requires only minimal +changes to apply to RISC-V also. The current arm64 implementation exits +early in a uniprocessor configuration by reading MPIDR & claiming that +uniprocessor can rely on the default values. + +This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: +topology: Stop using MPIDR for topology information")', because the +current code just assigns default values for multiprocessor systems. + +With the MPIDR references removed, store_cpu_topolgy() can be moved to +the common arch_topology code. + +Reviewed-by: Sudeep Holla +Acked-by: Catalin Marinas +Reviewed-by: Atish Patra +Signed-off-by: Conor Dooley +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/kernel/topology.c | 40 ---------------------------------------- + drivers/base/arch_topology.c | 19 +++++++++++++++++++ + 2 files changed, 19 insertions(+), 40 deletions(-) + +--- a/arch/arm64/kernel/topology.c ++++ b/arch/arm64/kernel/topology.c +@@ -22,46 +22,6 @@ + #include + #include + +-void store_cpu_topology(unsigned int cpuid) +-{ +- struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; +- u64 mpidr; +- +- if (cpuid_topo->package_id != -1) +- goto topology_populated; +- +- mpidr = read_cpuid_mpidr(); +- +- /* Uniprocessor systems can rely on default topology values */ +- if (mpidr & MPIDR_UP_BITMASK) +- return; +- +- /* +- * This would be the place to create cpu topology based on MPIDR. +- * +- * However, it cannot be trusted to depict the actual topology; some +- * pieces of the architecture enforce an artificial cap on Aff0 values +- * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an +- * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up +- * having absolutely no relationship to the actual underlying system +- * topology, and cannot be reasonably used as core / package ID. +- * +- * If the MT bit is set, Aff0 *could* be used to define a thread ID, but +- * we still wouldn't be able to obtain a sane core ID. This means we +- * need to entirely ignore MPIDR for any topology deduction. +- */ +- cpuid_topo->thread_id = -1; +- cpuid_topo->core_id = cpuid; +- cpuid_topo->package_id = cpu_to_node(cpuid); +- +- pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", +- cpuid, cpuid_topo->package_id, cpuid_topo->core_id, +- cpuid_topo->thread_id, mpidr); +- +-topology_populated: +- update_siblings_masks(cpuid); +-} +- + #ifdef CONFIG_ACPI + static bool __init acpi_cpu_is_threaded(int cpu) + { +--- a/drivers/base/arch_topology.c ++++ b/drivers/base/arch_topology.c +@@ -596,4 +596,23 @@ void __init init_cpu_topology(void) + else if (of_have_populated_dt() && parse_dt_topology()) + reset_cpu_topology(); + } ++ ++void store_cpu_topology(unsigned int cpuid) ++{ ++ struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; ++ ++ if (cpuid_topo->package_id != -1) ++ goto topology_populated; ++ ++ cpuid_topo->thread_id = -1; ++ cpuid_topo->core_id = cpuid; ++ cpuid_topo->package_id = cpu_to_node(cpuid); ++ ++ pr_debug("CPU%u: package %d core %d thread %d\n", ++ cpuid, cpuid_topo->package_id, cpuid_topo->core_id, ++ cpuid_topo->thread_id); ++ ++topology_populated: ++ update_siblings_masks(cpuid); ++} + #endif diff --git a/queue-5.10/riscv-topology-fix-default-topology-reporting.patch b/queue-5.10/riscv-topology-fix-default-topology-reporting.patch new file mode 100644 index 00000000000..a3db9fb3541 --- /dev/null +++ b/queue-5.10/riscv-topology-fix-default-topology-reporting.patch @@ -0,0 +1,87 @@ +From foo@baz Thu Oct 27 12:15:29 PM CEST 2022 +From: Conor Dooley +Date: Wed, 19 Oct 2022 13:53:03 +0100 +Subject: riscv: topology: fix default topology reporting +To: +Cc: , , , , , , , , , , , Atish Patra +Message-ID: <20221019125303.2845522-2-conor.dooley@microchip.com> + +From: Conor Dooley + +commit fbd92809997a391f28075f1c8b5ee314c225557c upstream. + +RISC-V has no sane defaults to fall back on where there is no cpu-map +in the devicetree. +Without sane defaults, the package, core and thread IDs are all set to +-1. This causes user-visible inaccuracies for tools like hwloc/lstopo +which rely on the sysfs cpu topology files to detect a system's +topology. + +On a PolarFire SoC, which should have 4 harts with a thread each, +lstopo currently reports: + +Machine (793MB total) + Package L#0 + NUMANode L#0 (P#0 793MB) + Core L#0 + L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0) + L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1) + L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2) + L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3) + +Adding calls to store_cpu_topology() in {boot,smp} hart bringup code +results in the correct topolgy being reported: + +Machine (793MB total) + Package L#0 + NUMANode L#0 (P#0 793MB) + L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) + L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) + L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2) + L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3) + +CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code +Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") +Reported-by: Brice Goglin +Link: https://github.com/open-mpi/hwloc/issues/536 +Reviewed-by: Sudeep Holla +Reviewed-by: Atish Patra +Signed-off-by: Conor Dooley +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/Kconfig | 2 +- + arch/riscv/kernel/smpboot.c | 4 +++- + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -35,7 +35,7 @@ config RISCV + select CLINT_TIMER if !MMU + select COMMON_CLK + select EDAC_SUPPORT +- select GENERIC_ARCH_TOPOLOGY if SMP ++ select GENERIC_ARCH_TOPOLOGY + select GENERIC_ATOMIC64 if !64BIT + select GENERIC_CLOCKEVENTS + select GENERIC_EARLY_IOREMAP +--- a/arch/riscv/kernel/smpboot.c ++++ b/arch/riscv/kernel/smpboot.c +@@ -46,6 +46,8 @@ void __init smp_prepare_cpus(unsigned in + int cpuid; + int ret; + ++ store_cpu_topology(smp_processor_id()); ++ + /* This covers non-smp usecase mandated by "nosmp" option */ + if (max_cpus == 0) + return; +@@ -152,8 +154,8 @@ asmlinkage __visible void smp_callin(voi + mmgrab(mm); + current->active_mm = mm; + ++ store_cpu_topology(curr_cpuid); + notify_cpu_starting(curr_cpuid); +- update_siblings_masks(curr_cpuid); + set_cpu_online(curr_cpuid, 1); + + /* diff --git a/queue-5.10/series b/queue-5.10/series index 306f6490c74..a0236a589c5 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -66,3 +66,6 @@ perf-pmu-validate-raw-event-with-sysfs-exported-form.patch perf-skip-and-warn-on-unknown-format-confign-attrs.patch fcntl-make-f_getown-ex-return-0-on-dead-owner-task.patch fcntl-fix-potential-deadlocks-for-fown_struct.lock.patch +arm64-dts-qcom-sc7180-trogdor-fixup-modem-memory-region.patch +arm64-topology-move-store_cpu_topology-to-shared-code.patch +riscv-topology-fix-default-topology-reporting.patch