From: Julian Seward <jseward@acm.org>
Date: Sat, 5 Feb 2005 18:24:47 +0000 (+0000)
Subject: A few more bits and pieces of amd64 instruction support.
X-Git-Tag: svn/VALGRIND_3_0_1^2~482
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=c61edd07ae003c30b7e62b8fa514d0fb9b0adecb;p=thirdparty%2Fvalgrind.git

A few more bits and pieces of amd64 instruction support.


git-svn-id: svn://svn.valgrind.org/vex/trunk@852
---

diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c
index 41554e0170..a86aeb0dcf 100644
--- a/VEX/priv/guest-amd64/toIR.c
+++ b/VEX/priv/guest-amd64/toIR.c
@@ -12481,13 +12481,13 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
          DIP("j%s-32 0x%llx\n", name_AMD64Condcode(opc - 0x80), d64);
          break;
 
-//..       /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */
-//.. 
-//..       case 0x31: /* RDTSC */
-//..          if (0) vex_printf("vex x86->IR: kludged rdtsc\n");
-//..          putIReg(4, R_EAX, mkU32(0));
-//..          putIReg(4, R_EDX, mkU32(0));
-//.. 
+      /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */
+
+      case 0x31: /* RDTSC */
+         if (1) vex_printf("vex amd64->IR: kludged rdtsc\n");
+         putIRegR( PFX_EMPTY, 4, R_RAX, mkU32(0));
+         putIRegR( PFX_EMPTY, 4, R_RDX, mkU32(0));
+
 //.. //--          t1 = newTemp(cb);
 //.. //--          t2 = newTemp(cb);
 //.. //--          t3 = newTemp(cb);
@@ -12508,9 +12508,9 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
 //.. //--          uInstr1(cb, POP,   4, TempReg, t3);
 //.. //--          uInstr2(cb, PUT,   4, TempReg, t3, ArchReg, R_EAX);
 //.. //--          uInstr0(cb, CALLM_E, 0);
-//..          DIP("rdtsc\n");
-//..          break;
-//.. 
+         DIP("rdtsc\n");
+         break;
+
 //..       /* =-=-=-=-=-=-=-=-=- PUSH/POP Sreg =-=-=-=-=-=-=-=-=-= */
 //.. 
 //..       case 0xA1: /* POP %FS */
diff --git a/VEX/priv/host-amd64/hdefs.c b/VEX/priv/host-amd64/hdefs.c
index 4e140eb1d2..b11f6706bf 100644
--- a/VEX/priv/host-amd64/hdefs.c
+++ b/VEX/priv/host-amd64/hdefs.c
@@ -2149,7 +2149,8 @@ vassert(0);
                              i->Ain.Alu64R.dst);
             goto done;
          case Armi_Mem:
-vassert(0);
+            *p++ = rexAMode_M( i->Ain.Alu64R.dst,
+                               i->Ain.Alu64R.src->Armi.Mem.am);
             *p++ = opc;
             p = doAMode_M(p, i->Ain.Alu64R.dst,
                              i->Ain.Alu64R.src->Armi.Mem.am);
diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index 2a90b1d256..e82de7d731 100644
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -771,8 +771,8 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
             aluOp = Aalu_SUB; break;
          case Iop_And8: case Iop_And16: case Iop_And32: case Iop_And64: 
             aluOp = Aalu_AND; break;
-//..          case Iop_Or8: case Iop_Or16: case Iop_Or32:  
-//..             aluOp = Xalu_OR; break;
+         case Iop_Or8: case Iop_Or16: case Iop_Or32: case Iop_Or64: 
+            aluOp = Aalu_OR; break;
 //..          case Iop_Xor8: case Iop_Xor16: case Iop_Xor32: 
 //..             aluOp = Xalu_XOR; break;
 //..          case Iop_Mul16: case Iop_Mul32: 
@@ -3231,11 +3231,11 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
       IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.STle.data);
       vassert(tya == Ity_I64);
       am = iselIntExpr_AMode(env, stmt->Ist.STle.addr);
-//..       if (tyd == Ity_I32) {
-//..          X86RI* ri = iselIntExpr_RI(env, stmt->Ist.STle.data);
-//..          addInstr(env, X86Instr_Alu32M(Xalu_MOV,ri,am));
-//..          return;
-//..       }
+      if (tyd == Ity_I64) {
+         AMD64RI* ri = iselIntExpr_RI(env, stmt->Ist.STle.data);
+         addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,ri,am));
+         return;
+      }
       if (tyd == Ity_I8 || tyd == Ity_I16 || tyd == Ity_I32) {
          HReg r = iselIntExpr_R(env, stmt->Ist.STle.data);
          addInstr(env, AMD64Instr_Store(tyd==Ity_I8 ? 1 : (tyd==Ity_I16 ? 2 : 4),