From: Greg Kroah-Hartman Date: Mon, 20 Jul 2020 09:55:24 +0000 (+0200) Subject: 5.7-stable patches X-Git-Tag: v4.4.231~37 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=c7b4ab70ef2267fd2fa2b71b56b00b0456d57a0c;p=thirdparty%2Fkernel%2Fstable-queue.git 5.7-stable patches added patches: apparmor-ensure-that-dfa-state-tables-have-entries.patch arm-dts-mt7623-add-phy-mode-property-for-gmac2.patch clk-qcom-add-missing-msm8998-ufs_unipro_core_clk_src.patch dmaengine-ti-k3-udma-disable-memcopy-via-mcu-navss-on-am654.patch habanalabs-align-protection-bits-configuration-of-all-tpcs.patch pci-pm-call-.bridge_d3-hook-only-if-non-null.patch perf-stat-zero-all-the-ena-and-run-array-slot-stats-for-interval-mode.patch rdma-mlx5-verify-that-qp-is-created-with-rq-or-sq.patch rdma-rxe-set-default-vendor-id.patch samples-fix-binderfs-sample.patch soc-qcom-rpmh-invalidate-sleep-and-wake-tcses-before-flushing-new-data.patch soc-qcom-rpmh-rsc-allow-using-free-wake-tcs-for-active-request.patch soc-qcom-rpmh-rsc-clear-active-mode-configuration-for-wake-tcs.patch soc-qcom-rpmh-update-dirty-flag-only-when-data-changes.patch soc-qcom-socinfo-add-missing-soc_id-sysfs-entry.patch --- diff --git a/queue-5.7/apparmor-ensure-that-dfa-state-tables-have-entries.patch b/queue-5.7/apparmor-ensure-that-dfa-state-tables-have-entries.patch new file mode 100644 index 00000000000..64fed46a0be --- /dev/null +++ b/queue-5.7/apparmor-ensure-that-dfa-state-tables-have-entries.patch @@ -0,0 +1,44 @@ +From c27c6bd2c4d6b6bb779f9b722d5607993e1d5e5c Mon Sep 17 00:00:00 2001 +From: John Johansen +Date: Mon, 30 Mar 2020 23:37:54 -0700 +Subject: apparmor: ensure that dfa state tables have entries + +From: John Johansen + +commit c27c6bd2c4d6b6bb779f9b722d5607993e1d5e5c upstream. + +Currently it is possible to specify a state machine table with 0 length, +this is not valid as optional tables are specified by not defining +the table as present. Further this allows by-passing the base tables +range check against the next/check tables. + +Fixes: d901d6a298dc ("apparmor: dfa split verification of table headers") +Reported-by: Mike Salvatore +Signed-off-by: John Johansen +Signed-off-by: Greg Kroah-Hartman + +--- + security/apparmor/match.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/security/apparmor/match.c ++++ b/security/apparmor/match.c +@@ -97,6 +97,9 @@ static struct table_header *unpack_table + th.td_flags == YYTD_DATA8)) + goto out; + ++ /* if we have a table it must have some entries */ ++ if (th.td_lolen == 0) ++ goto out; + tsize = table_size(th.td_lolen, th.td_flags); + if (bsize < tsize) + goto out; +@@ -198,6 +201,8 @@ static int verify_dfa(struct aa_dfa *dfa + + state_count = dfa->tables[YYTD_ID_BASE]->td_lolen; + trans_count = dfa->tables[YYTD_ID_NXT]->td_lolen; ++ if (state_count == 0) ++ goto out; + for (i = 0; i < state_count; i++) { + if (!(BASE_TABLE(dfa)[i] & MATCH_FLAG_DIFF_ENCODE) && + (DEFAULT_TABLE(dfa)[i] >= state_count)) diff --git a/queue-5.7/arm-dts-mt7623-add-phy-mode-property-for-gmac2.patch b/queue-5.7/arm-dts-mt7623-add-phy-mode-property-for-gmac2.patch new file mode 100644 index 00000000000..e22166fb362 --- /dev/null +++ b/queue-5.7/arm-dts-mt7623-add-phy-mode-property-for-gmac2.patch @@ -0,0 +1,31 @@ +From ff5b89c2858f28006f9f9c0a88c55a679488192c Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Sun, 8 Mar 2020 14:34:37 +0800 +Subject: arm: dts: mt7623: add phy-mode property for gmac2 + +From: Sean Wang + +commit ff5b89c2858f28006f9f9c0a88c55a679488192c upstream. + +Add phy-mode property required by phylink on gmac2 + +Fixes: b8fc9f30821e ("net: ethernet: mediatek: Add basic PHYLINK support") +Signed-off-by: Sean Wang +Link: https://lore.kernel.org/r/70e3eff31ecd500ed4862d9de28325a4dbd15105.1583648927.git.sean.wang@mediatek.com +Signed-off-by: Matthias Brugger +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts ++++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +@@ -138,6 +138,7 @@ + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; ++ phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + diff --git a/queue-5.7/clk-qcom-add-missing-msm8998-ufs_unipro_core_clk_src.patch b/queue-5.7/clk-qcom-add-missing-msm8998-ufs_unipro_core_clk_src.patch new file mode 100644 index 00000000000..0a47cf0f22e --- /dev/null +++ b/queue-5.7/clk-qcom-add-missing-msm8998-ufs_unipro_core_clk_src.patch @@ -0,0 +1,83 @@ +From b1e8d713e6b2d59ee3a7b57c0dab88a19ec0cf33 Mon Sep 17 00:00:00 2001 +From: Jeffrey Hugo +Date: Thu, 28 May 2020 07:22:05 -0700 +Subject: clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src + +From: Jeffrey Hugo + +commit b1e8d713e6b2d59ee3a7b57c0dab88a19ec0cf33 upstream. + +ufs_unipro_core_clk_src is required to allow UFS to clock scale for power +savings. + +Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") +Signed-off-by: Jeffrey Hugo +Link: https://lkml.kernel.org/r/20200528142205.44003-1-jeffrey.l.hugo@gmail.com +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/clk/qcom/gcc-msm8998.c | 27 +++++++++++++++++++++++++++ + include/dt-bindings/clock/qcom,gcc-msm8998.h | 1 + + 2 files changed, 28 insertions(+) + +--- a/drivers/clk/qcom/gcc-msm8998.c ++++ b/drivers/clk/qcom/gcc-msm8998.c +@@ -1110,6 +1110,27 @@ static struct clk_rcg2 ufs_axi_clk_src = + }, + }; + ++static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { ++ F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), ++ F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), ++ F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 ufs_unipro_core_clk_src = { ++ .cmd_rcgr = 0x76028, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_parent_map_0, ++ .freq_tbl = ftbl_ufs_unipro_core_clk_src, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "ufs_unipro_core_clk_src", ++ .parent_names = gcc_parent_names_0, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ + static const struct freq_tbl ftbl_usb30_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), +@@ -2549,6 +2570,11 @@ static struct clk_branch gcc_ufs_unipro_ + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_clk", ++ .parent_names = (const char *[]){ ++ "ufs_unipro_core_clk_src", ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +@@ -2904,6 +2930,7 @@ static struct clk_regmap *gcc_msm8998_cl + [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, + [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, + [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, ++ [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, +--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h ++++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h +@@ -183,6 +183,7 @@ + #define GCC_MSS_SNOC_AXI_CLK 174 + #define GCC_MSS_MNOC_BIMC_AXI_CLK 175 + #define GCC_BIMC_GFX_CLK 176 ++#define UFS_UNIPRO_CORE_CLK_SRC 177 + + #define PCIE_0_GDSC 0 + #define UFS_GDSC 1 diff --git a/queue-5.7/dmaengine-ti-k3-udma-disable-memcopy-via-mcu-navss-on-am654.patch b/queue-5.7/dmaengine-ti-k3-udma-disable-memcopy-via-mcu-navss-on-am654.patch new file mode 100644 index 00000000000..b9337405f15 --- /dev/null +++ b/queue-5.7/dmaengine-ti-k3-udma-disable-memcopy-via-mcu-navss-on-am654.patch @@ -0,0 +1,33 @@ +From a4e688535a0829980d5ef1516c0713777a874c62 Mon Sep 17 00:00:00 2001 +From: Peter Ujfalusi +Date: Fri, 27 Mar 2020 16:42:28 +0200 +Subject: dmaengine: ti: k3-udma: Disable memcopy via MCU NAVSS on am654 + +From: Peter Ujfalusi + +commit a4e688535a0829980d5ef1516c0713777a874c62 upstream. + +Trace of a test for DMA memcpy domains slipped into the glue layer commit. +The memcpy support should be disabled on the MCU UDMAP. + +Fixes: d702419134133 ("dmaengine: ti: k3-udma: Add glue layer for non DMAengine users") +Signed-off-by: Peter Ujfalusi +Link: https://lore.kernel.org/r/20200327144228.11101-1-peter.ujfalusi@ti.com +Signed-off-by: Vinod Koul +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/dma/ti/k3-udma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/dma/ti/k3-udma.c ++++ b/drivers/dma/ti/k3-udma.c +@@ -3186,7 +3186,7 @@ static struct udma_match_data am654_main + + static struct udma_match_data am654_mcu_data = { + .psil_base = 0x6000, +- .enable_memcpy_support = true, /* TEST: DMA domains */ ++ .enable_memcpy_support = false, + .statictr_z_mask = GENMASK(11, 0), + .rchan_oes_offset = 0x2000, + .tpl_levels = 2, diff --git a/queue-5.7/habanalabs-align-protection-bits-configuration-of-all-tpcs.patch b/queue-5.7/habanalabs-align-protection-bits-configuration-of-all-tpcs.patch new file mode 100644 index 00000000000..6c6115ded83 --- /dev/null +++ b/queue-5.7/habanalabs-align-protection-bits-configuration-of-all-tpcs.patch @@ -0,0 +1,229 @@ +From 79c823c57e69d9e584a5ee4ee6406eb3854393ae Mon Sep 17 00:00:00 2001 +From: Tomer Tayar +Date: Wed, 1 Apr 2020 19:30:29 +0300 +Subject: habanalabs: Align protection bits configuration of all TPCs + +From: Tomer Tayar + +commit 79c823c57e69d9e584a5ee4ee6406eb3854393ae upstream. + +Align the protection bits configuration of all TPC cores to be as of TPC +core 0. + +Fixes: a513f9a7eca5 ("habanalabs: make tpc registers secured") + +Signed-off-by: Tomer Tayar +Reviewed-by: Oded Gabbay +Signed-off-by: Oded Gabbay +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/misc/habanalabs/goya/goya_security.c | 99 ++++++++++++++++++++++++++- + 1 file changed, 98 insertions(+), 1 deletion(-) + +--- a/drivers/misc/habanalabs/goya/goya_security.c ++++ b/drivers/misc/habanalabs/goya/goya_security.c +@@ -695,7 +695,6 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); +- mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); +@@ -875,6 +874,16 @@ static void goya_init_tpc_protection_bit + goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE); + ++ pb_addr = (mmTPC1_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; ++ word_offset = ((mmTPC1_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; ++ ++ mask = 1 << ((mmTPC1_CFG_SEMAPHORE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); ++ ++ WREG32(pb_addr + word_offset, ~mask); ++ + pb_addr = (mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; +@@ -882,6 +891,10 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + +@@ -1057,6 +1070,16 @@ static void goya_init_tpc_protection_bit + goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE); + ++ pb_addr = (mmTPC2_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; ++ word_offset = ((mmTPC2_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; ++ ++ mask = 1 << ((mmTPC2_CFG_SEMAPHORE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); ++ ++ WREG32(pb_addr + word_offset, ~mask); ++ + pb_addr = (mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; +@@ -1064,6 +1087,10 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + +@@ -1239,6 +1266,16 @@ static void goya_init_tpc_protection_bit + goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE); + ++ pb_addr = (mmTPC3_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; ++ word_offset = ((mmTPC3_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; ++ ++ mask = 1 << ((mmTPC3_CFG_SEMAPHORE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); ++ ++ WREG32(pb_addr + word_offset, ~mask); ++ + pb_addr = (mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH + & PROT_BITS_OFFS) >> 7) << 2; +@@ -1246,6 +1283,10 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + +@@ -1421,6 +1462,16 @@ static void goya_init_tpc_protection_bit + goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE); + ++ pb_addr = (mmTPC4_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; ++ word_offset = ((mmTPC4_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; ++ ++ mask = 1 << ((mmTPC4_CFG_SEMAPHORE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); ++ ++ WREG32(pb_addr + word_offset, ~mask); ++ + pb_addr = (mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; +@@ -1428,6 +1479,10 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + +@@ -1603,6 +1658,16 @@ static void goya_init_tpc_protection_bit + goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE); + ++ pb_addr = (mmTPC5_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; ++ word_offset = ((mmTPC5_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; ++ ++ mask = 1 << ((mmTPC5_CFG_SEMAPHORE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); ++ ++ WREG32(pb_addr + word_offset, ~mask); ++ + pb_addr = (mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; +@@ -1610,6 +1675,10 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + +@@ -1785,6 +1854,16 @@ static void goya_init_tpc_protection_bit + goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE); + ++ pb_addr = (mmTPC6_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; ++ word_offset = ((mmTPC6_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; ++ ++ mask = 1 << ((mmTPC6_CFG_SEMAPHORE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); ++ ++ WREG32(pb_addr + word_offset, ~mask); ++ + pb_addr = (mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; +@@ -1792,6 +1871,10 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + +@@ -1967,6 +2050,16 @@ static void goya_init_tpc_protection_bit + goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE); + goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE); + ++ pb_addr = (mmTPC7_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; ++ word_offset = ((mmTPC7_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; ++ ++ mask = 1 << ((mmTPC7_CFG_SEMAPHORE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); ++ ++ WREG32(pb_addr + word_offset, ~mask); ++ + pb_addr = (mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & + PROT_BITS_OFFS) >> 7) << 2; +@@ -1974,6 +2067,10 @@ static void goya_init_tpc_protection_bit + mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); ++ mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + diff --git a/queue-5.7/pci-pm-call-.bridge_d3-hook-only-if-non-null.patch b/queue-5.7/pci-pm-call-.bridge_d3-hook-only-if-non-null.patch new file mode 100644 index 00000000000..ab595ad41a2 --- /dev/null +++ b/queue-5.7/pci-pm-call-.bridge_d3-hook-only-if-non-null.patch @@ -0,0 +1,41 @@ +From c3aaf086701d05a82c8156ee8620af41e5a7d6fe Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Tue, 7 Apr 2020 18:23:15 -0500 +Subject: PCI/PM: Call .bridge_d3() hook only if non-NULL + +From: Bjorn Helgaas + +commit c3aaf086701d05a82c8156ee8620af41e5a7d6fe upstream. + +26ad34d510a8 ("PCI / ACPI: Whitelist D3 for more PCIe hotplug ports") added +the struct pci_platform_pm_ops.bridge_d3() function pointer and +platform_pci_bridge_d3() to use it. + +The .bridge_d3() op is implemented by acpi_pci_platform_pm, but not by +mid_pci_platform_pm. We don't expect platform_pci_bridge_d3() to be called +on Intel MID platforms, but nothing in the code itself would prevent that. + +Check the .bridge_d3() pointer for NULL before calling it. + +Fixes: 26ad34d510a8 ("PCI / ACPI: Whitelist D3 for more PCIe hotplug ports") +Signed-off-by: Bjorn Helgaas +Reviewed-by: Mika Westerberg +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/pci.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/pci/pci.c ++++ b/drivers/pci/pci.c +@@ -868,7 +868,9 @@ static inline bool platform_pci_need_res + + static inline bool platform_pci_bridge_d3(struct pci_dev *dev) + { +- return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false; ++ if (pci_platform_pm && pci_platform_pm->bridge_d3) ++ return pci_platform_pm->bridge_d3(dev); ++ return false; + } + + /** diff --git a/queue-5.7/perf-stat-zero-all-the-ena-and-run-array-slot-stats-for-interval-mode.patch b/queue-5.7/perf-stat-zero-all-the-ena-and-run-array-slot-stats-for-interval-mode.patch new file mode 100644 index 00000000000..1f00183e06d --- /dev/null +++ b/queue-5.7/perf-stat-zero-all-the-ena-and-run-array-slot-stats-for-interval-mode.patch @@ -0,0 +1,49 @@ +From 0e0bf1ea1147fcf74eab19c2d3c853cc3740a72f Mon Sep 17 00:00:00 2001 +From: Jin Yao +Date: Thu, 9 Apr 2020 15:07:55 +0800 +Subject: perf stat: Zero all the 'ena' and 'run' array slot stats for interval mode + +From: Jin Yao + +commit 0e0bf1ea1147fcf74eab19c2d3c853cc3740a72f upstream. + +As the code comments in perf_stat_process_counter() say, we calculate +counter's data every interval, and the display code shows ps->res_stats +avg value. We need to zero the stats for interval mode. + +But the current code only zeros the res_stats[0], it doesn't zero the +res_stats[1] and res_stats[2], which are for ena and run of counter. + +This patch zeros the whole res_stats[] for interval mode. + +Fixes: 51fd2df1e882 ("perf stat: Fix interval output values") +Signed-off-by: Jin Yao +Cc: Alexander Shishkin +Cc: Andi Kleen +Cc: Jin Yao +Cc: Jiri Olsa +Cc: Kan Liang +Cc: Peter Zijlstra +Link: http://lore.kernel.org/lkml/20200409070755.17261-1-yao.jin@linux.intel.com +Signed-off-by: Arnaldo Carvalho de Melo +Signed-off-by: Greg Kroah-Hartman + +--- + tools/perf/util/stat.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/tools/perf/util/stat.c ++++ b/tools/perf/util/stat.c +@@ -368,8 +368,10 @@ int perf_stat_process_counter(struct per + * interval mode, otherwise overall avg running + * averages will be shown for each interval. + */ +- if (config->interval) +- init_stats(ps->res_stats); ++ if (config->interval) { ++ for (i = 0; i < 3; i++) ++ init_stats(&ps->res_stats[i]); ++ } + + if (counter->per_pkg) + zero_per_pkg(counter); diff --git a/queue-5.7/rdma-mlx5-verify-that-qp-is-created-with-rq-or-sq.patch b/queue-5.7/rdma-mlx5-verify-that-qp-is-created-with-rq-or-sq.patch new file mode 100644 index 00000000000..bf2d1cde7a0 --- /dev/null +++ b/queue-5.7/rdma-mlx5-verify-that-qp-is-created-with-rq-or-sq.patch @@ -0,0 +1,35 @@ +From 0eacc574aae7300bf46c10c7116c3ba5825505b7 Mon Sep 17 00:00:00 2001 +From: Aharon Landau +Date: Mon, 27 Apr 2020 18:46:36 +0300 +Subject: RDMA/mlx5: Verify that QP is created with RQ or SQ + +From: Aharon Landau + +commit 0eacc574aae7300bf46c10c7116c3ba5825505b7 upstream. + +RAW packet QP and underlay QP must be created with either +RQ or SQ, check that. + +Fixes: e126ba97dba9 ("mlx5: Add driver for Mellanox Connect-IB adapters") +Link: https://lore.kernel.org/r/20200427154636.381474-37-leon@kernel.org +Signed-off-by: Aharon Landau +Reviewed-by: Maor Gottlieb +Signed-off-by: Leon Romanovsky +Signed-off-by: Jason Gunthorpe +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/infiniband/hw/mlx5/qp.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/infiniband/hw/mlx5/qp.c ++++ b/drivers/infiniband/hw/mlx5/qp.c +@@ -1525,6 +1525,8 @@ static int create_raw_packet_qp(struct m + u16 uid = to_mpd(pd)->uid; + u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; + ++ if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) ++ return -EINVAL; + if (qp->sq.wqe_cnt) { + err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); + if (err) diff --git a/queue-5.7/rdma-rxe-set-default-vendor-id.patch b/queue-5.7/rdma-rxe-set-default-vendor-id.patch new file mode 100644 index 00000000000..5f7b6f9dbd5 --- /dev/null +++ b/queue-5.7/rdma-rxe-set-default-vendor-id.patch @@ -0,0 +1,80 @@ +From 0184afd15a141d7ce24c32c0d86a1e3ba6bc0eb3 Mon Sep 17 00:00:00 2001 +From: Zhu Yanjun +Date: Mon, 6 Apr 2020 20:35:01 +0300 +Subject: RDMA/rxe: Set default vendor ID + +From: Zhu Yanjun + +commit 0184afd15a141d7ce24c32c0d86a1e3ba6bc0eb3 upstream. + +The RXE driver doesn't set vendor_id and user space applications see +zeros. This causes to pyverbs tests to fail with the following traceback, +because the expectation is to have valid vendor_id. + +Traceback (most recent call last): + File "tests/test_device.py", line 51, in test_query_device + self.verify_device_attr(attr) + File "tests/test_device.py", line 77, in verify_device_attr + assert attr.vendor_id != 0 + +In order to fix it, we will set vendor_id 0XFFFFFF, according to the IBTA +v1.4 A3.3.1 VENDOR INFORMATION section. + +""" +A vendor that produces a generic controller (i.e., one that supports a +standard I/O protocol such as SRP), which does not have vendor specific +device drivers, may use the value of 0xFFFFFF in the VendorID field. +""" + +Before: + +hca_id: rxe0 + transport: InfiniBand (0) + fw_ver: 0.0.0 + node_guid: 5054:00ff:feaa:5363 + sys_image_guid: 5054:00ff:feaa:5363 + vendor_id: 0x0000 + +After: + +hca_id: rxe0 + transport: InfiniBand (0) + fw_ver: 0.0.0 + node_guid: 5054:00ff:feaa:5363 + sys_image_guid: 5054:00ff:feaa:5363 + vendor_id: 0xffffff + +Fixes: 8700e3e7c485 ("Soft RoCE driver") +Link: https://lore.kernel.org/r/20200406173501.1466273-1-leon@kernel.org +Signed-off-by: Zhu Yanjun +Signed-off-by: Leon Romanovsky +Signed-off-by: Jason Gunthorpe +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/infiniband/sw/rxe/rxe.c | 1 + + drivers/infiniband/sw/rxe/rxe_param.h | 3 +++ + 2 files changed, 4 insertions(+) + +--- a/drivers/infiniband/sw/rxe/rxe.c ++++ b/drivers/infiniband/sw/rxe/rxe.c +@@ -77,6 +77,7 @@ static void rxe_init_device_param(struct + { + rxe->max_inline_data = RXE_MAX_INLINE_DATA; + ++ rxe->attr.vendor_id = RXE_VENDOR_ID; + rxe->attr.max_mr_size = RXE_MAX_MR_SIZE; + rxe->attr.page_size_cap = RXE_PAGE_SIZE_CAP; + rxe->attr.max_qp = RXE_MAX_QP; +--- a/drivers/infiniband/sw/rxe/rxe_param.h ++++ b/drivers/infiniband/sw/rxe/rxe_param.h +@@ -127,6 +127,9 @@ enum rxe_device_param { + + /* Delay before calling arbiter timer */ + RXE_NSEC_ARB_TIMER_DELAY = 200, ++ ++ /* IBTA v1.4 A3.3.1 VENDOR INFORMATION section */ ++ RXE_VENDOR_ID = 0XFFFFFF, + }; + + /* default/initial rxe port parameters */ diff --git a/queue-5.7/samples-fix-binderfs-sample.patch b/queue-5.7/samples-fix-binderfs-sample.patch new file mode 100644 index 00000000000..9b93ff2cc52 --- /dev/null +++ b/queue-5.7/samples-fix-binderfs-sample.patch @@ -0,0 +1,50 @@ +From c624adc9cb6e6e8f1c0230a7775add700bc2409b Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Tue, 28 Apr 2020 23:25:33 +0200 +Subject: samples: fix binderfs sample + +From: Arnd Bergmann + +commit c624adc9cb6e6e8f1c0230a7775add700bc2409b upstream. + +A routine check for misspelled Kconfig symbols showed on instance +from last year, the correct symbol name is CONFIG_ANDROID_BINDERFS, +not CONFIG_CONFIG_ANDROID_BINDERFS, so the extra prefix must +be removed in the Kconfig file to allow enabling the sample. + +As the actual sample fails to build as a kernel module, change the +Makefile enough to get to build as a hostprog instead. + +Fixes: 9762dc1432e1 ("samples: add binderfs sample program") +Signed-off-by: Arnd Bergmann +Acked-by: Christian Brauner +Link: https://lore.kernel.org/r/20200428212555.2806258-1-arnd@arndb.de +Signed-off-by: Jonathan Corbet +Signed-off-by: Greg Kroah-Hartman + +--- + samples/Kconfig | 2 +- + samples/binderfs/Makefile | 6 +++++- + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/samples/Kconfig ++++ b/samples/Kconfig +@@ -171,7 +171,7 @@ config SAMPLE_VFIO_MDEV_MBOCHS + + config SAMPLE_ANDROID_BINDERFS + bool "Build Android binderfs example" +- depends on CONFIG_ANDROID_BINDERFS ++ depends on ANDROID_BINDERFS + help + Builds a sample program to illustrate the use of the Android binderfs + filesystem. +--- a/samples/binderfs/Makefile ++++ b/samples/binderfs/Makefile +@@ -1,2 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-$(CONFIG_SAMPLE_ANDROID_BINDERFS) += binderfs_example.o ++ifndef CROSS_COMPILE ++ifdef CONFIG_SAMPLE_ANDROID_BINDERFS ++hostprogs := binderfs_example ++endif ++endif diff --git a/queue-5.7/series b/queue-5.7/series index 8bfb5f2ffca..8dadfa49c4d 100644 --- a/queue-5.7/series +++ b/queue-5.7/series @@ -115,3 +115,18 @@ keys-asymmetric-fix-error-return-code-in-software_ke.patch nvme-explicitly-update-mpath-disk-capacity-on-revali.patch regmap-debugfs-don-t-sleep-while-atomic-for-fast_io-.patch copy_xstate_to_kernel-fix-typo-which-caused-gdb-regression.patch +arm-dts-mt7623-add-phy-mode-property-for-gmac2.patch +soc-qcom-socinfo-add-missing-soc_id-sysfs-entry.patch +dmaengine-ti-k3-udma-disable-memcopy-via-mcu-navss-on-am654.patch +apparmor-ensure-that-dfa-state-tables-have-entries.patch +habanalabs-align-protection-bits-configuration-of-all-tpcs.patch +rdma-rxe-set-default-vendor-id.patch +pci-pm-call-.bridge_d3-hook-only-if-non-null.patch +perf-stat-zero-all-the-ena-and-run-array-slot-stats-for-interval-mode.patch +soc-qcom-rpmh-update-dirty-flag-only-when-data-changes.patch +soc-qcom-rpmh-invalidate-sleep-and-wake-tcses-before-flushing-new-data.patch +soc-qcom-rpmh-rsc-clear-active-mode-configuration-for-wake-tcs.patch +soc-qcom-rpmh-rsc-allow-using-free-wake-tcs-for-active-request.patch +samples-fix-binderfs-sample.patch +rdma-mlx5-verify-that-qp-is-created-with-rq-or-sq.patch +clk-qcom-add-missing-msm8998-ufs_unipro_core_clk_src.patch diff --git a/queue-5.7/soc-qcom-rpmh-invalidate-sleep-and-wake-tcses-before-flushing-new-data.patch b/queue-5.7/soc-qcom-rpmh-invalidate-sleep-and-wake-tcses-before-flushing-new-data.patch new file mode 100644 index 00000000000..e39b9dde4d6 --- /dev/null +++ b/queue-5.7/soc-qcom-rpmh-invalidate-sleep-and-wake-tcses-before-flushing-new-data.patch @@ -0,0 +1,103 @@ +From f5ac95f9ca2f439179a5baf48e1c0f22f83d936e Mon Sep 17 00:00:00 2001 +From: Maulik Shah +Date: Sun, 12 Apr 2020 20:20:01 +0530 +Subject: soc: qcom: rpmh: Invalidate SLEEP and WAKE TCSes before flushing new data + +From: Maulik Shah + +commit f5ac95f9ca2f439179a5baf48e1c0f22f83d936e upstream. + +TCSes have previously programmed data when rpmh_flush() is called. +This can cause old data to trigger along with newly flushed. + +Fix this by cleaning SLEEP and WAKE TCSes before new data is flushed. + +With this there is no need to invoke rpmh_rsc_invalidate() call from +rpmh_invalidate(). + +Simplify rpmh_invalidate() by moving invalidate_batch() inside. + +Fixes: 600513dfeef3 ("drivers: qcom: rpmh: cache sleep/wake state requests") +Signed-off-by: Maulik Shah +Reviewed-by: Douglas Anderson +Reviewed-by: Stephen Boyd +Link: https://lore.kernel.org/r/1586703004-13674-4-git-send-email-mkshah@codeaurora.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/soc/qcom/rpmh.c | 41 ++++++++++++++++++----------------------- + 1 file changed, 18 insertions(+), 23 deletions(-) + +--- a/drivers/soc/qcom/rpmh.c ++++ b/drivers/soc/qcom/rpmh.c +@@ -317,19 +317,6 @@ static int flush_batch(struct rpmh_ctrlr + return ret; + } + +-static void invalidate_batch(struct rpmh_ctrlr *ctrlr) +-{ +- struct batch_cache_req *req, *tmp; +- unsigned long flags; +- +- spin_lock_irqsave(&ctrlr->cache_lock, flags); +- list_for_each_entry_safe(req, tmp, &ctrlr->batch_cache, list) +- kfree(req); +- INIT_LIST_HEAD(&ctrlr->batch_cache); +- ctrlr->dirty = true; +- spin_unlock_irqrestore(&ctrlr->cache_lock, flags); +-} +- + /** + * rpmh_write_batch: Write multiple sets of RPMH commands and wait for the + * batch to finish. +@@ -467,6 +454,13 @@ int rpmh_flush(struct rpmh_ctrlr *ctrlr) + return 0; + } + ++ /* Invalidate the TCSes first to avoid stale data */ ++ do { ++ ret = rpmh_rsc_invalidate(ctrlr_to_drv(ctrlr)); ++ } while (ret == -EAGAIN); ++ if (ret) ++ return ret; ++ + /* First flush the cached batch requests */ + ret = flush_batch(ctrlr); + if (ret) +@@ -498,24 +492,25 @@ int rpmh_flush(struct rpmh_ctrlr *ctrlr) + } + + /** +- * rpmh_invalidate: Invalidate all sleep and active sets +- * sets. ++ * rpmh_invalidate: Invalidate sleep and wake sets in batch_cache + * + * @dev: The device making the request + * +- * Invalidate the sleep and active values in the TCS blocks. ++ * Invalidate the sleep and wake values in batch_cache. + */ + int rpmh_invalidate(const struct device *dev) + { + struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr(dev); +- int ret; +- +- invalidate_batch(ctrlr); ++ struct batch_cache_req *req, *tmp; ++ unsigned long flags; + +- do { +- ret = rpmh_rsc_invalidate(ctrlr_to_drv(ctrlr)); +- } while (ret == -EAGAIN); ++ spin_lock_irqsave(&ctrlr->cache_lock, flags); ++ list_for_each_entry_safe(req, tmp, &ctrlr->batch_cache, list) ++ kfree(req); ++ INIT_LIST_HEAD(&ctrlr->batch_cache); ++ ctrlr->dirty = true; ++ spin_unlock_irqrestore(&ctrlr->cache_lock, flags); + +- return ret; ++ return 0; + } + EXPORT_SYMBOL(rpmh_invalidate); diff --git a/queue-5.7/soc-qcom-rpmh-rsc-allow-using-free-wake-tcs-for-active-request.patch b/queue-5.7/soc-qcom-rpmh-rsc-allow-using-free-wake-tcs-for-active-request.patch new file mode 100644 index 00000000000..3decd672df0 --- /dev/null +++ b/queue-5.7/soc-qcom-rpmh-rsc-allow-using-free-wake-tcs-for-active-request.patch @@ -0,0 +1,80 @@ +From 38427e5a47bf83299da930bd474c6cb2632ad810 Mon Sep 17 00:00:00 2001 +From: Maulik Shah +Date: Sun, 12 Apr 2020 20:20:04 +0530 +Subject: soc: qcom: rpmh-rsc: Allow using free WAKE TCS for active request + +From: Maulik Shah + +commit 38427e5a47bf83299da930bd474c6cb2632ad810 upstream. + +When there are more than one WAKE TCS available and there is no dedicated +ACTIVE TCS available, invalidating all WAKE TCSes and waiting for current +transfer to complete in first WAKE TCS blocks using another free WAKE TCS +to complete current request. + +Remove rpmh_rsc_invalidate() to happen from tcs_write() when WAKE TCSes +is re-purposed to be used for Active mode. Clear only currently used +WAKE TCS's register configuration. + +Fixes: 2de4b8d33eab (drivers: qcom: rpmh-rsc: allow active requests from wake TCS) +Signed-off-by: Maulik Shah +Reviewed-by: Douglas Anderson +Reviewed-by: Stephen Boyd +Link: https://lore.kernel.org/r/1586703004-13674-7-git-send-email-mkshah@codeaurora.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/soc/qcom/rpmh-rsc.c | 23 +++++++++++------------ + 1 file changed, 11 insertions(+), 12 deletions(-) + +--- a/drivers/soc/qcom/rpmh-rsc.c ++++ b/drivers/soc/qcom/rpmh-rsc.c +@@ -148,7 +148,7 @@ int rpmh_rsc_invalidate(struct rsc_drv * + static struct tcs_group *get_tcs_for_msg(struct rsc_drv *drv, + const struct tcs_request *msg) + { +- int type, ret; ++ int type; + struct tcs_group *tcs; + + switch (msg->state) { +@@ -169,19 +169,10 @@ static struct tcs_group *get_tcs_for_msg + * If we are making an active request on a RSC that does not have a + * dedicated TCS for active state use, then re-purpose a wake TCS to + * send active votes. +- * NOTE: The driver must be aware that this RSC does not have a +- * dedicated AMC, and therefore would invalidate the sleep and wake +- * TCSes before making an active state request. + */ + tcs = get_tcs_of_type(drv, type); +- if (msg->state == RPMH_ACTIVE_ONLY_STATE && !tcs->num_tcs) { ++ if (msg->state == RPMH_ACTIVE_ONLY_STATE && !tcs->num_tcs) + tcs = get_tcs_of_type(drv, WAKE_TCS); +- if (tcs->num_tcs) { +- ret = rpmh_rsc_invalidate(drv); +- if (ret) +- return ERR_PTR(ret); +- } +- } + + return tcs; + } +@@ -406,8 +397,16 @@ static int tcs_write(struct rsc_drv *drv + + tcs->req[tcs_id - tcs->offset] = msg; + set_bit(tcs_id, drv->tcs_in_use); +- if (msg->state == RPMH_ACTIVE_ONLY_STATE && tcs->type != ACTIVE_TCS) ++ if (msg->state == RPMH_ACTIVE_ONLY_STATE && tcs->type != ACTIVE_TCS) { ++ /* ++ * Clear previously programmed WAKE commands in selected ++ * repurposed TCS to avoid triggering them. tcs->slots will be ++ * cleaned from rpmh_flush() by invoking rpmh_rsc_invalidate() ++ */ ++ write_tcs_reg_sync(drv, RSC_DRV_CMD_ENABLE, tcs_id, 0); ++ write_tcs_reg_sync(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, tcs_id, 0); + enable_tcs_irq(drv, tcs_id, true); ++ } + spin_unlock(&drv->lock); + + __tcs_buffer_write(drv, tcs_id, 0, msg); diff --git a/queue-5.7/soc-qcom-rpmh-rsc-clear-active-mode-configuration-for-wake-tcs.patch b/queue-5.7/soc-qcom-rpmh-rsc-clear-active-mode-configuration-for-wake-tcs.patch new file mode 100644 index 00000000000..3c34ecb3e0b --- /dev/null +++ b/queue-5.7/soc-qcom-rpmh-rsc-clear-active-mode-configuration-for-wake-tcs.patch @@ -0,0 +1,148 @@ +From 15b3bf61b8d48f8e0ccd9d7f1bcb468b543da396 Mon Sep 17 00:00:00 2001 +From: "Raju P.L.S.S.S.N" +Date: Sun, 12 Apr 2020 20:20:03 +0530 +Subject: soc: qcom: rpmh-rsc: Clear active mode configuration for wake TCS + +From: Raju P.L.S.S.S.N + +commit 15b3bf61b8d48f8e0ccd9d7f1bcb468b543da396 upstream. + +For RSCs that have sleep & wake TCS but no dedicated active TCS, wake +TCS can be re-purposed to send active requests. Once the active requests +are sent and response is received, the active mode configuration needs +to be cleared so that controller can use wake TCS for sending wake +requests. + +Introduce enable_tcs_irq() to enable completion IRQ for repurposed TCSes. + +Fixes: 2de4b8d33eab (drivers: qcom: rpmh-rsc: allow active requests from wake TCS) +Signed-off-by: Raju P.L.S.S.S.N +[mkshah: call enable_tcs_irq() within drv->lock, update commit message] +Signed-off-by: Maulik Shah +Reviewed-by: Douglas Anderson +Reviewed-by: Stephen Boyd +Link: https://lore.kernel.org/r/1586703004-13674-6-git-send-email-mkshah@codeaurora.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/soc/qcom/rpmh-rsc.c | 77 ++++++++++++++++++++++++++++++-------------- + 1 file changed, 54 insertions(+), 23 deletions(-) + +--- a/drivers/soc/qcom/rpmh-rsc.c ++++ b/drivers/soc/qcom/rpmh-rsc.c +@@ -201,6 +201,42 @@ static const struct tcs_request *get_req + return NULL; + } + ++static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) ++{ ++ u32 enable; ++ ++ /* ++ * HW req: Clear the DRV_CONTROL and enable TCS again ++ * While clearing ensure that the AMC mode trigger is cleared ++ * and then the mode enable is cleared. ++ */ ++ enable = read_tcs_reg(drv, RSC_DRV_CONTROL, tcs_id, 0); ++ enable &= ~TCS_AMC_MODE_TRIGGER; ++ write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); ++ enable &= ~TCS_AMC_MODE_ENABLE; ++ write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); ++ ++ if (trigger) { ++ /* Enable the AMC mode on the TCS and then trigger the TCS */ ++ enable = TCS_AMC_MODE_ENABLE; ++ write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); ++ enable |= TCS_AMC_MODE_TRIGGER; ++ write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); ++ } ++} ++ ++static void enable_tcs_irq(struct rsc_drv *drv, int tcs_id, bool enable) ++{ ++ u32 data; ++ ++ data = read_tcs_reg(drv, RSC_DRV_IRQ_ENABLE, 0, 0); ++ if (enable) ++ data |= BIT(tcs_id); ++ else ++ data &= ~BIT(tcs_id); ++ write_tcs_reg(drv, RSC_DRV_IRQ_ENABLE, 0, data); ++} ++ + /** + * tcs_tx_done: TX Done interrupt handler + */ +@@ -237,6 +273,14 @@ static irqreturn_t tcs_tx_done(int irq, + } + + trace_rpmh_tx_done(drv, i, req, err); ++ ++ /* ++ * If wake tcs was re-purposed for sending active ++ * votes, clear AMC trigger & enable modes and ++ * disable interrupt for this TCS ++ */ ++ if (!drv->tcs[ACTIVE_TCS].num_tcs) ++ __tcs_set_trigger(drv, i, false); + skip: + /* Reclaim the TCS */ + write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i, 0); +@@ -244,6 +288,13 @@ skip: + write_tcs_reg(drv, RSC_DRV_IRQ_CLEAR, 0, BIT(i)); + spin_lock(&drv->lock); + clear_bit(i, drv->tcs_in_use); ++ /* ++ * Disable interrupt for WAKE TCS to avoid being ++ * spammed with interrupts coming when the solver ++ * sends its wake votes. ++ */ ++ if (!drv->tcs[ACTIVE_TCS].num_tcs) ++ enable_tcs_irq(drv, i, false); + spin_unlock(&drv->lock); + if (req) + rpmh_tx_done(req, err); +@@ -285,28 +336,6 @@ static void __tcs_buffer_write(struct rs + write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, tcs_id, cmd_enable); + } + +-static void __tcs_trigger(struct rsc_drv *drv, int tcs_id) +-{ +- u32 enable; +- +- /* +- * HW req: Clear the DRV_CONTROL and enable TCS again +- * While clearing ensure that the AMC mode trigger is cleared +- * and then the mode enable is cleared. +- */ +- enable = read_tcs_reg(drv, RSC_DRV_CONTROL, tcs_id, 0); +- enable &= ~TCS_AMC_MODE_TRIGGER; +- write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); +- enable &= ~TCS_AMC_MODE_ENABLE; +- write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); +- +- /* Enable the AMC mode on the TCS and then trigger the TCS */ +- enable = TCS_AMC_MODE_ENABLE; +- write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); +- enable |= TCS_AMC_MODE_TRIGGER; +- write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); +-} +- + static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs, + const struct tcs_request *msg) + { +@@ -377,10 +406,12 @@ static int tcs_write(struct rsc_drv *drv + + tcs->req[tcs_id - tcs->offset] = msg; + set_bit(tcs_id, drv->tcs_in_use); ++ if (msg->state == RPMH_ACTIVE_ONLY_STATE && tcs->type != ACTIVE_TCS) ++ enable_tcs_irq(drv, tcs_id, true); + spin_unlock(&drv->lock); + + __tcs_buffer_write(drv, tcs_id, 0, msg); +- __tcs_trigger(drv, tcs_id); ++ __tcs_set_trigger(drv, tcs_id, true); + + done_write: + spin_unlock_irqrestore(&tcs->lock, flags); diff --git a/queue-5.7/soc-qcom-rpmh-update-dirty-flag-only-when-data-changes.patch b/queue-5.7/soc-qcom-rpmh-update-dirty-flag-only-when-data-changes.patch new file mode 100644 index 00000000000..a4475f953a3 --- /dev/null +++ b/queue-5.7/soc-qcom-rpmh-update-dirty-flag-only-when-data-changes.patch @@ -0,0 +1,101 @@ +From bb7000677a1b287206c8d4327c62442fa3050a8f Mon Sep 17 00:00:00 2001 +From: Maulik Shah +Date: Sun, 12 Apr 2020 20:20:00 +0530 +Subject: soc: qcom: rpmh: Update dirty flag only when data changes + +From: Maulik Shah + +commit bb7000677a1b287206c8d4327c62442fa3050a8f upstream. + +Currently rpmh ctrlr dirty flag is set for all cases regardless of data +is really changed or not. Add changes to update dirty flag when data is +changed to newer values. Update dirty flag everytime when data in batch +cache is updated since rpmh_flush() may get invoked from any CPU instead +of only last CPU going to low power mode. + +Also move dirty flag updates to happen from within cache_lock and remove +unnecessary INIT_LIST_HEAD() call and a default case from switch. + +Fixes: 600513dfeef3 ("drivers: qcom: rpmh: cache sleep/wake state requests") +Signed-off-by: Maulik Shah +Reviewed-by: Srinivas Rao L +Reviewed-by: Evan Green +Reviewed-by: Douglas Anderson +Reviewed-by: Stephen Boyd +Link: https://lore.kernel.org/r/1586703004-13674-3-git-send-email-mkshah@codeaurora.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/soc/qcom/rpmh.c | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +--- a/drivers/soc/qcom/rpmh.c ++++ b/drivers/soc/qcom/rpmh.c +@@ -119,6 +119,7 @@ static struct cache_req *cache_rpm_reque + { + struct cache_req *req; + unsigned long flags; ++ u32 old_sleep_val, old_wake_val; + + spin_lock_irqsave(&ctrlr->cache_lock, flags); + req = __find_req(ctrlr, cmd->addr); +@@ -133,26 +134,27 @@ static struct cache_req *cache_rpm_reque + + req->addr = cmd->addr; + req->sleep_val = req->wake_val = UINT_MAX; +- INIT_LIST_HEAD(&req->list); + list_add_tail(&req->list, &ctrlr->cache); + + existing: ++ old_sleep_val = req->sleep_val; ++ old_wake_val = req->wake_val; ++ + switch (state) { + case RPMH_ACTIVE_ONLY_STATE: +- if (req->sleep_val != UINT_MAX) +- req->wake_val = cmd->data; +- break; + case RPMH_WAKE_ONLY_STATE: + req->wake_val = cmd->data; + break; + case RPMH_SLEEP_STATE: + req->sleep_val = cmd->data; + break; +- default: +- break; + } + +- ctrlr->dirty = true; ++ ctrlr->dirty = (req->sleep_val != old_sleep_val || ++ req->wake_val != old_wake_val) && ++ req->sleep_val != UINT_MAX && ++ req->wake_val != UINT_MAX; ++ + unlock: + spin_unlock_irqrestore(&ctrlr->cache_lock, flags); + +@@ -287,6 +289,7 @@ static void cache_batch(struct rpmh_ctrl + + spin_lock_irqsave(&ctrlr->cache_lock, flags); + list_add_tail(&req->list, &ctrlr->batch_cache); ++ ctrlr->dirty = true; + spin_unlock_irqrestore(&ctrlr->cache_lock, flags); + } + +@@ -323,6 +326,7 @@ static void invalidate_batch(struct rpmh + list_for_each_entry_safe(req, tmp, &ctrlr->batch_cache, list) + kfree(req); + INIT_LIST_HEAD(&ctrlr->batch_cache); ++ ctrlr->dirty = true; + spin_unlock_irqrestore(&ctrlr->cache_lock, flags); + } + +@@ -507,7 +511,6 @@ int rpmh_invalidate(const struct device + int ret; + + invalidate_batch(ctrlr); +- ctrlr->dirty = true; + + do { + ret = rpmh_rsc_invalidate(ctrlr_to_drv(ctrlr)); diff --git a/queue-5.7/soc-qcom-socinfo-add-missing-soc_id-sysfs-entry.patch b/queue-5.7/soc-qcom-socinfo-add-missing-soc_id-sysfs-entry.patch new file mode 100644 index 00000000000..e78f1f3ca3a --- /dev/null +++ b/queue-5.7/soc-qcom-socinfo-add-missing-soc_id-sysfs-entry.patch @@ -0,0 +1,37 @@ +From 27a344139c186889d742764d3c2a62b395949cef Mon Sep 17 00:00:00 2001 +From: Srinivas Kandagatla +Date: Thu, 19 Mar 2020 12:14:18 +0000 +Subject: soc: qcom: socinfo: add missing soc_id sysfs entry + +From: Srinivas Kandagatla + +commit 27a344139c186889d742764d3c2a62b395949cef upstream. + +Looks like SoC ID is not exported to sysfs for some reason. +This patch adds it! + +This is mostly used by userspace libraries like Snapdragon +Neural Processing Engine (SNPE) SDK for checking supported SoC info. + +Fixes: efb448d0a3fc ("soc: qcom: Add socinfo driver") +Reviewed-by: Stephen Boyd +Signed-off-by: Srinivas Kandagatla +Link: https://lore.kernel.org/r/20200319121418.5180-1-srinivas.kandagatla@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/soc/qcom/socinfo.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/soc/qcom/socinfo.c ++++ b/drivers/soc/qcom/socinfo.c +@@ -430,6 +430,8 @@ static int qcom_socinfo_probe(struct pla + qs->attr.family = "Snapdragon"; + qs->attr.machine = socinfo_machine(&pdev->dev, + le32_to_cpu(info->id)); ++ qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u", ++ le32_to_cpu(info->id)); + qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u", + SOCINFO_MAJOR(le32_to_cpu(info->ver)), + SOCINFO_MINOR(le32_to_cpu(info->ver)));