From: Pan Li Date: Mon, 27 Apr 2026 02:01:52 +0000 (+0800) Subject: RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=cb3ca149a51be12f835df60b88e830aea35a3bbd;p=thirdparty%2Fgcc.git RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost This patch would like to combine the vec_duplicate + vmsgtu.vv to the vmsgtu.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the GR2VR cost is greater than zero. Assume we have asm code like below, GR2VR cost is 0. Before this patch: 11 beq a3,zero,.L8 12 vsetvli a5,zero,e32,m1,ta,ma 13 vmv.v.x v2,a2 ... 16 .L3: 17 vsetvli a5,a3,e32,m1,ta,ma ... 22 vmsgtu.vv v1,v2,v3 ... 25 bne a3,zero,.L3 After this patch: 11 beq a3,zero,.L8 ... 14 .L3: 15 vsetvli a5,a3,e32,m1,ta,ma ... 20 vmsgtu.vx v1,a2,v3 ... 23 bne a3,zero,.L3 gcc/ChangeLog: * config/riscv/predicates.md: Add ltu to swappable cmp operator. * config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Handle the swapped rtx code as well. Signed-off-by: Pan Li --- diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8022c84b114..4116674601c 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -612,7 +612,7 @@ (match_code "eq,ne,le,leu,gt,gtu,lt,ltu")) (define_predicate "comparison_swappable_operator" - (match_code "gtu,gt,geu,ge")) + (match_code "gtu,gt,geu,ge,ltu")) (define_predicate "ge_operator" (match_code "ge,geu")) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index cfea5dd693e..3c7e749cb60 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -6073,6 +6073,8 @@ get_swapped_cmp_rtx_code (rtx_code code) return LEU; case GE: return LE; + case LTU: + return GTU; default: gcc_unreachable (); }