From: Jerome Brunet Date: Mon, 13 May 2019 12:31:11 +0000 (+0200) Subject: clk: meson: axg: spread spectrum is on mpll2 X-Git-Tag: v4.19.99~256 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=cbd69e7ae16d41c3079409e4f1861246e9655dbd;p=thirdparty%2Fkernel%2Fstable.git clk: meson: axg: spread spectrum is on mpll2 [ Upstream commit dc4e62d373f881cbf51513296a6db7806516a01a ] After testing, it appears that the SSEN bit controls the spread spectrum function on MPLL2, not MPLL0. Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet Signed-off-by: Sasha Levin --- diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 02229d051d778..4e7dac24948b8 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -461,11 +461,6 @@ static struct clk_regmap axg_mpll0_div = { .shift = 16, .width = 9, }, - .ssen = { - .reg_off = HHI_MPLL_CNTL, - .shift = 25, - .width = 1, - }, .misc = { .reg_off = HHI_PLL_TOP_MISC, .shift = 0, @@ -560,6 +555,11 @@ static struct clk_regmap axg_mpll2_div = { .shift = 16, .width = 9, }, + .ssen = { + .reg_off = HHI_MPLL_CNTL, + .shift = 25, + .width = 1, + }, .misc = { .reg_off = HHI_PLL_TOP_MISC, .shift = 2,