From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 10 Feb 2026 12:50:59 +0000 (+0000)
Subject: serial: amba-pl011: Enable UART in earlycon setup
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=cc8de922bb8e3f4349e355de72bf2b3ef840c430;p=thirdparty%2Fkernel%2Flinux.git

serial: amba-pl011: Enable UART in earlycon setup

Currently the PL011 driver only enables the UART (by setting UARTEN
in REG_CR) in pl011_startup(), so if it is used for earlycon it is
relying on the bootrom/firmware having left the UART enabled.

There's no particular reason not to actively enable the UART before
using it for earlycon, and the earlycon handling for e.g. the 8250
UART sets up the UART in its setup function, so follow that in the
PL011.

This allows use of earlycon with a UART that the firmware hasn't
already been using for its own output, but the main motivation is
that QEMU will otherwise log a message complaining that the guest is
trying to write to a UART it never enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://patch.msgid.link/20260210125100.223138-1-peter.maydell@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 7f17d288c807..462a8c380059 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2701,18 +2701,47 @@ static int pl011_early_read(struct console *con, char *s, unsigned int n)
 static int __init pl011_early_console_setup(struct earlycon_device *device,
 					    const char *opt)
 {
+	unsigned int cr;
+
 	if (!device->port.membase)
 		return -ENODEV;
 
 	device->con->write = pl011_early_write;
 	device->con->read = pl011_early_read;
 
+	if (device->port.iotype == UPIO_MEM32)
+		cr = readl(device->port.membase + UART011_CR);
+	else
+		cr = readw(device->port.membase + UART011_CR);
+	cr &= UART011_CR_RTS | UART011_CR_DTR;
+	cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
+	if (device->port.iotype == UPIO_MEM32)
+		writel(cr, device->port.membase + UART011_CR);
+	else
+		writew(cr, device->port.membase + UART011_CR);
+
 	return 0;
 }
 
 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
 
-OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
+/*
+ * The SBSA UART has no defined control register and is assumed to
+ * be pre-enabled by firmware, so we do not write to UART011_CR.
+ */
+static int __init sbsa_uart_early_console_setup(struct earlycon_device *device,
+						const char *opt)
+{
+	if (!device->port.membase)
+		return -ENODEV;
+
+	device->con->write = pl011_early_write;
+	device->con->read = pl011_early_read;
+
+	return 0;
+}
+
+OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", sbsa_uart_early_console_setup);
 
 /*
  * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by