From: Jiawei <jiawei@iscas.ac.cn>
Date: Tue, 30 Jun 2026 16:24:20 +0000 (+0800)
Subject: RISC-V: Fix zvdota altfmt disassemble format issue
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=cd28fb866379c5dbbe431feb24aa62d369554f80;p=thirdparty%2Fbinutils-gdb.git

RISC-V: Fix zvdota altfmt disassemble format issue

Fix-up vtype altfmt disassembly extension check.

Only print the altfmt vtype names when the object advertises one of the
extensions that defines that encoding, or when disassembling with all
extensions enabled.

Validated with:
  make check RUNTEST=... RUNTESTFLAGS="riscv.exp"

Result:
  PASS: gas/riscv/vector-insns
  PASS: gas/riscv/zvdota
  # of expected passes: 360

gas/ChangeLog:

	* testsuite/gas/riscv/zvdota.d: Fix format.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_vtype_altfmt_supported): Add ext check.
	(print_insn_args): Use altfmt check.
---

diff --git a/gas/testsuite/gas/riscv/zvdota.d b/gas/testsuite/gas/riscv/zvdota.d
index 8d133255993..b60142b1a9a 100644
--- a/gas/testsuite/gas/riscv/zvdota.d
+++ b/gas/testsuite/gas/riscv/zvdota.d
@@ -12,8 +12,8 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+928f9877[ 	]+vfwdota.vv[ 	]+v16,v8,v31
 [ 	]+[0-9a-f]+:[ 	]+9a8f9877[ 	]+vfqwdota.vv[ 	]+v16,v8,v31
 [ 	]+[0-9a-f]+:[ 	]+9e8f9877[ 	]+vfqwdota.alt.vv[ 	]+v16,v8,v31
-[ 	]+[0-9a-f]+:[ 	]+988f8877[ 	]+vqwdotau.vv[ 	]+v16,v8,v31
-[ 	]+[0-9a-f]+:[ 	]+9c8f8877[ 	]+vqwdotas.vv[ 	]+v16,v8,v31
-[ 	]+[0-9a-f]+:[ 	]+928f9877[ 	]+vfwdota.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+988f8877[ 	]+vqwdotau.vv[ 	]+v16,v8,v31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9c8f8877[ 	]+vqwdotas.vv[ 	]+v16,v8,v31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+908f9877[ 	]+vfwdota.vv[ 	]+v16,v8,v31,v0.t
 [ 	]+[0-9a-f]+:[ 	]+980f9877[ 	]+vfqwdota.vv[ 	]+v16,v0,v31,v0.t
 [ 	]+[0-9a-f]+:[ 	]+9c0f9877[ 	]+vfqwdota.alt.vv[ 	]+v16,v0,v31,v0.t
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 724c8b90b12..e5a9e66f2e2 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -107,6 +107,22 @@ parse_riscv_dis_option_without_args (const char *option,
   return true;
 }
 
+static bool
+riscv_vtype_altfmt_supported (struct riscv_private_data *pd)
+{
+  return (pd->all_ext
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvfbfa")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvfofp8min")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvfqwbdota8f")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvfqwdota8f")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvfwbdota16bf")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvfwdota16bf")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvqwbdota8i")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvqwbdota16i")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvqwdota8i")
+	  || riscv_subset_supports (&pd->riscv_rps_dis, "zvqwdota16i"));
+}
+
 /* Parse RISC-V disassembler option (possibly with arguments).  */
 
 static void
@@ -466,6 +482,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
 		unsigned int imm_vtype_altfmt
 		  = EXTRACT_OPERAND (VTYPE_ALTFMT, imm);
+		bool imm_vtype_altfmt_supported
+		  = (imm_vtype_altfmt
+		     && riscv_vtype_altfmt_supported (pd));
 		unsigned int imm_vtype_res = (imm >> 9);
 
 		if (imm_vsew < ARRAY_SIZE (riscv_vsew)
@@ -474,7 +493,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		    && imm_vma < ARRAY_SIZE (riscv_vma)
 		    && !imm_vtype_res
 		    && (imm_vtype_altfmt == 0
-			|| imm_vsew < ARRAY_SIZE (riscv_vsew_altfmt))
+			|| (imm_vtype_altfmt_supported
+			    && imm_vsew < ARRAY_SIZE (riscv_vsew_altfmt)))
 		    && riscv_vsew[imm_vsew] != NULL
 		    && riscv_vlmul[imm_vlmul] != NULL)
 		  print (info->stream, dis_style_text, "%s,%s,%s,%s",