From: Alfie Richards Date: Thu, 23 Oct 2025 09:45:22 +0000 (+0000) Subject: aarch64: gas: Allow movprfx with fmmla and bfscale [PR gas/33562] X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=cec7ab85f2470c820d34442d88ed05ed2268e7f7;p=thirdparty%2Fbinutils-gdb.git aarch64: gas: Allow movprfx with fmmla and bfscale [PR gas/33562] These instructions were previously incorrectly marked as not accepting movprfx. Fix this and add tests. PR gas/33562 opcodes: * aarch64-tbl.h: Update widening fmmmla and bfscale instructions. gas: * testsuite/gas/aarch64/f8f16mm_sve2-bad.l: Update test with movprfx. * testsuite/gas/aarch64/f8f16mm_sve2.d: Ditto. * testsuite/gas/aarch64/f8f16mm_sve2.s: Ditto. * testsuite/gas/aarch64/f8f32mm_sve2-bad.l: Ditto. * testsuite/gas/aarch64/f8f32mm_sve2.d: Ditto. * testsuite/gas/aarch64/f8f32mm_sve2.s: Ditto. * testsuite/gas/aarch64/sve-f16f32mm-bad.l: Ditto. * testsuite/gas/aarch64/sve-f16f32mm.d: Ditto. * testsuite/gas/aarch64/sve-f16f32mm.s: Ditto. * testsuite/gas/aarch64/sve-bfscale-sve2.s: Ditto. * testsuite/gas/aarch64/sve-bfscale-sve2.d: Ditto. Approved-By: Alice Carlotti --- diff --git a/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l b/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l index 3560c17e415..797abd00f01 100644 --- a/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l +++ b/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l @@ -7,3 +7,19 @@ .*: Error: selected processor does not support `fmmla z31.h,z0.b,z31.b' .*: Error: selected processor does not support `fmmla z31.h,z31.b,z0.b' .*: Error: selected processor does not support `fmmla z31.h,z31.b,z31.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.h,z1.b,z1.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.h,z1.b,z31.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.h,z31.b,z1.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.h,z31.b,z31.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.h,z0.b,z0.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.h,z0.b,z30.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.h,z30.b,z0.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.h,z30.b,z30.b' diff --git a/gas/testsuite/gas/aarch64/f8f16mm_sve2.d b/gas/testsuite/gas/aarch64/f8f16mm_sve2.d index 3bb69ceafae..dccc3a1a277 100644 --- a/gas/testsuite/gas/aarch64/f8f16mm_sve2.d +++ b/gas/testsuite/gas/aarch64/f8f16mm_sve2.d @@ -16,3 +16,21 @@ Disassembly of section .*: .*: 647fe01f fmmla z31.h, z0.b, z31.b .*: 6460e3ff fmmla z31.h, z31.b, z0.b .*: 647fe3ff fmmla z31.h, z31.b, z31.b + +.* : +.*: 0420bde0 movprfx z0, z15 +.*: 6461e020 fmmla z0.h, z1.b, z1.b +.*: 0420bde0 movprfx z0, z15 +.*: 647fe020 fmmla z0.h, z1.b, z31.b +.*: 0420bde0 movprfx z0, z15 +.*: 6461e3e0 fmmla z0.h, z31.b, z1.b +.*: 0420bde0 movprfx z0, z15 +.*: 647fe3e0 fmmla z0.h, z31.b, z31.b +.*: 0420bdff movprfx z31, z15 +.*: 6460e01f fmmla z31.h, z0.b, z0.b +.*: 0420bdff movprfx z31, z15 +.*: 647ee01f fmmla z31.h, z0.b, z30.b +.*: 0420bdff movprfx z31, z15 +.*: 6460e3df fmmla z31.h, z30.b, z0.b +.*: 0420bdff movprfx z31, z15 +.*: 647ee3df fmmla z31.h, z30.b, z30.b diff --git a/gas/testsuite/gas/aarch64/f8f16mm_sve2.s b/gas/testsuite/gas/aarch64/f8f16mm_sve2.s index c1a32c98c09..5ea3b8266fb 100644 --- a/gas/testsuite/gas/aarch64/f8f16mm_sve2.s +++ b/gas/testsuite/gas/aarch64/f8f16mm_sve2.s @@ -7,3 +7,21 @@ a: fmmla z31.h, z0.b, z31.b fmmla z31.h, z31.b, z0.b fmmla z31.h, z31.b, z31.b + +b: + movprfx z0, z15 + fmmla z0.h, z1.b, z1.b + movprfx z0, z15 + fmmla z0.h, z1.b, z31.b + movprfx z0, z15 + fmmla z0.h, z31.b, z1.b + movprfx z0, z15 + fmmla z0.h, z31.b, z31.b + movprfx z31, z15 + fmmla z31.h, z0.b, z0.b + movprfx z31, z15 + fmmla z31.h, z0.b, z30.b + movprfx z31, z15 + fmmla z31.h, z30.b, z0.b + movprfx z31, z15 + fmmla z31.h, z30.b, z30.b diff --git a/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l b/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l index 46b62b2736c..5982bb76978 100644 --- a/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l +++ b/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l @@ -7,3 +7,19 @@ .*: Error: selected processor does not support `fmmla z31.s,z0.b,z31.b' .*: Error: selected processor does not support `fmmla z31.s,z31.b,z0.b' .*: Error: selected processor does not support `fmmla z31.s,z31.b,z31.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z1.b,z1.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z1.b,z31.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z31.b,z1.b' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z31.b,z31.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z0.b,z0.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z0.b,z30.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z30.b,z0.b' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z30.b,z30.b' diff --git a/gas/testsuite/gas/aarch64/f8f32mm_sve2.d b/gas/testsuite/gas/aarch64/f8f32mm_sve2.d index 30670c989a4..eec87127916 100644 --- a/gas/testsuite/gas/aarch64/f8f32mm_sve2.d +++ b/gas/testsuite/gas/aarch64/f8f32mm_sve2.d @@ -16,3 +16,21 @@ Disassembly of section .*: .*: 643fe01f fmmla z31.s, z0.b, z31.b .*: 6420e3ff fmmla z31.s, z31.b, z0.b .*: 643fe3ff fmmla z31.s, z31.b, z31.b + +.* : +.*: 0420bde0 movprfx z0, z15 +.*: 6421e020 fmmla z0.s, z1.b, z1.b +.*: 0420bde0 movprfx z0, z15 +.*: 643fe020 fmmla z0.s, z1.b, z31.b +.*: 0420bde0 movprfx z0, z15 +.*: 6421e3e0 fmmla z0.s, z31.b, z1.b +.*: 0420bde0 movprfx z0, z15 +.*: 643fe3e0 fmmla z0.s, z31.b, z31.b +.*: 0420bdff movprfx z31, z15 +.*: 6420e01f fmmla z31.s, z0.b, z0.b +.*: 0420bdff movprfx z31, z15 +.*: 643ee01f fmmla z31.s, z0.b, z30.b +.*: 0420bdff movprfx z31, z15 +.*: 6420e3df fmmla z31.s, z30.b, z0.b +.*: 0420bdff movprfx z31, z15 +.*: 643ee3df fmmla z31.s, z30.b, z30.b diff --git a/gas/testsuite/gas/aarch64/f8f32mm_sve2.s b/gas/testsuite/gas/aarch64/f8f32mm_sve2.s index a293e3f1391..31ccd15b86a 100644 --- a/gas/testsuite/gas/aarch64/f8f32mm_sve2.s +++ b/gas/testsuite/gas/aarch64/f8f32mm_sve2.s @@ -7,3 +7,21 @@ a: fmmla z31.s, z0.b, z31.b fmmla z31.s, z31.b, z0.b fmmla z31.s, z31.b, z31.b + +b: + movprfx z0, z15 + fmmla z0.s, z1.b, z1.b + movprfx z0, z15 + fmmla z0.s, z1.b, z31.b + movprfx z0, z15 + fmmla z0.s, z31.b, z1.b + movprfx z0, z15 + fmmla z0.s, z31.b, z31.b + movprfx z31, z15 + fmmla z31.s, z0.b, z0.b + movprfx z31, z15 + fmmla z31.s, z0.b, z30.b + movprfx z31, z15 + fmmla z31.s, z30.b, z0.b + movprfx z31, z15 + fmmla z31.s, z30.b, z30.b diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sve2.d b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.d index 874dda04fe7..c8a077cb82d 100644 --- a/gas/testsuite/gas/aarch64/sve-bfscale-sve2.d +++ b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.d @@ -16,3 +16,35 @@ Disassembly of section .*: .*: 650983ff bfscale z31.h, p0/m, z31.h, z31.h .*: 65099c1f bfscale z31.h, p7/m, z31.h, z0.h .*: 65099fff bfscale z31.h, p7/m, z31.h, z31.h +.*: 0420bde0 movprfx z0, z15 +.*: 65098020 bfscale z0.h, p0/m, z0.h, z1.h +.*: 0420bde0 movprfx z0, z15 +.*: 650983e0 bfscale z0.h, p0/m, z0.h, z31.h +.*: 0420bde0 movprfx z0, z15 +.*: 65099c20 bfscale z0.h, p7/m, z0.h, z1.h +.*: 0420bde0 movprfx z0, z15 +.*: 65099fe0 bfscale z0.h, p7/m, z0.h, z31.h +.*: 0420bdff movprfx z31, z15 +.*: 6509801f bfscale z31.h, p0/m, z31.h, z0.h +.*: 0420bdff movprfx z31, z15 +.*: 650983df bfscale z31.h, p0/m, z31.h, z30.h +.*: 0420bdff movprfx z31, z15 +.*: 65099c1f bfscale z31.h, p7/m, z31.h, z0.h +.*: 0420bdff movprfx z31, z15 +.*: 65099fdf bfscale z31.h, p7/m, z31.h, z30.h +.*: 045021e0 movprfx z0.h, p0/z, z15.h +.*: 65098020 bfscale z0.h, p0/m, z0.h, z1.h +.*: 045121e0 movprfx z0.h, p0/m, z15.h +.*: 650983e0 bfscale z0.h, p0/m, z0.h, z31.h +.*: 04503de0 movprfx z0.h, p7/z, z15.h +.*: 65099c20 bfscale z0.h, p7/m, z0.h, z1.h +.*: 04513de0 movprfx z0.h, p7/m, z15.h +.*: 65099fe0 bfscale z0.h, p7/m, z0.h, z31.h +.*: 045021ff movprfx z31.h, p0/z, z15.h +.*: 6509801f bfscale z31.h, p0/m, z31.h, z0.h +.*: 045121ff movprfx z31.h, p0/m, z15.h +.*: 650983df bfscale z31.h, p0/m, z31.h, z30.h +.*: 04503dff movprfx z31.h, p7/z, z15.h +.*: 65099c1f bfscale z31.h, p7/m, z31.h, z0.h +.*: 04513dff movprfx z31.h, p7/m, z15.h +.*: 65099fdf bfscale z31.h, p7/m, z31.h, z30.h diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sve2.s b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.s index 33155242a23..9ab195ceda9 100644 --- a/gas/testsuite/gas/aarch64/sve-bfscale-sve2.s +++ b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.s @@ -7,3 +7,37 @@ bfscale: bfscale z31.h, p0/m, z31.h, z31.h bfscale z31.h, p7/m, z31.h, z0.h bfscale z31.h, p7/m, z31.h, z31.h + + movprfx z0, z15 + bfscale z0.h, p0/m, z0.h, z1.h + movprfx z0, z15 + bfscale z0.h, p0/m, z0.h, z31.h + movprfx z0, z15 + bfscale z0.h, p7/m, z0.h, z1.h + movprfx z0, z15 + bfscale z0.h, p7/m, z0.h, z31.h + movprfx z31, z15 + bfscale z31.h, p0/m, z31.h, z0.h + movprfx z31, z15 + bfscale z31.h, p0/m, z31.h, z30.h + movprfx z31, z15 + bfscale z31.h, p7/m, z31.h, z0.h + movprfx z31, z15 + bfscale z31.h, p7/m, z31.h, z30.h + + movprfx z0.h, p0/z, z15.h + bfscale z0.h, p0/m, z0.h, z1.h + movprfx z0.h, p0/m, z15.h + bfscale z0.h, p0/m, z0.h, z31.h + movprfx z0.h, p7/z, z15.h + bfscale z0.h, p7/m, z0.h, z1.h + movprfx z0.h, p7/m, z15.h + bfscale z0.h, p7/m, z0.h, z31.h + movprfx z31.h, p0/z, z15.h + bfscale z31.h, p0/m, z31.h, z0.h + movprfx z31.h, p0/m, z15.h + bfscale z31.h, p0/m, z31.h, z30.h + movprfx z31.h, p7/z, z15.h + bfscale z31.h, p7/m, z31.h, z0.h + movprfx z31.h, p7/m, z15.h + bfscale z31.h, p7/m, z31.h, z30.h diff --git a/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l b/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l index bb955681bae..215a1bb7b36 100644 --- a/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l +++ b/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l @@ -7,3 +7,19 @@ .*: Error: selected processor does not support `fmmla z31.s,z0.h,z31.h' .*: Error: selected processor does not support `fmmla z31.s,z31.h,z0.h' .*: Error: selected processor does not support `fmmla z31.s,z31.h,z31.h' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z1.h,z1.h' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z1.h,z31.h' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z31.h,z1.h' +.*: Error: selected processor does not support `movprfx z0,z15' +.*: Error: selected processor does not support `fmmla z0.s,z31.h,z31.h' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z0.h,z0.h' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z0.h,z30.h' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z30.h,z0.h' +.*: Error: selected processor does not support `movprfx z31,z15' +.*: Error: selected processor does not support `fmmla z31.s,z30.h,z30.h' diff --git a/gas/testsuite/gas/aarch64/sve-f16f32mm.d b/gas/testsuite/gas/aarch64/sve-f16f32mm.d index 8b72bf2b681..5760ec8ee6d 100644 --- a/gas/testsuite/gas/aarch64/sve-f16f32mm.d +++ b/gas/testsuite/gas/aarch64/sve-f16f32mm.d @@ -16,3 +16,21 @@ Disassembly of section .*: .*: 643fe41f fmmla z31.s, z0.h, z31.h .*: 6420e7ff fmmla z31.s, z31.h, z0.h .*: 643fe7ff fmmla z31.s, z31.h, z31.h + +.* : +.*: 0420bde0 movprfx z0, z15 +.*: 6421e420 fmmla z0.s, z1.h, z1.h +.*: 0420bde0 movprfx z0, z15 +.*: 643fe420 fmmla z0.s, z1.h, z31.h +.*: 0420bde0 movprfx z0, z15 +.*: 6421e7e0 fmmla z0.s, z31.h, z1.h +.*: 0420bde0 movprfx z0, z15 +.*: 643fe7e0 fmmla z0.s, z31.h, z31.h +.*: 0420bdff movprfx z31, z15 +.*: 6420e41f fmmla z31.s, z0.h, z0.h +.*: 0420bdff movprfx z31, z15 +.*: 643ee41f fmmla z31.s, z0.h, z30.h +.*: 0420bdff movprfx z31, z15 +.*: 6420e7df fmmla z31.s, z30.h, z0.h +.*: 0420bdff movprfx z31, z15 +.*: 643ee7df fmmla z31.s, z30.h, z30.h diff --git a/gas/testsuite/gas/aarch64/sve-f16f32mm.s b/gas/testsuite/gas/aarch64/sve-f16f32mm.s index 49792581aa8..eb96a106364 100644 --- a/gas/testsuite/gas/aarch64/sve-f16f32mm.s +++ b/gas/testsuite/gas/aarch64/sve-f16f32mm.s @@ -7,3 +7,21 @@ a: fmmla z31.s, z0.h, z31.h fmmla z31.s, z31.h, z0.h fmmla z31.s, z31.h, z31.h + +b: + movprfx z0, z15 + fmmla z0.s, z1.h, z1.h + movprfx z0, z15 + fmmla z0.s, z1.h, z31.h + movprfx z0, z15 + fmmla z0.s, z31.h, z1.h + movprfx z0, z15 + fmmla z0.s, z31.h, z31.h + movprfx z31, z15 + fmmla z31.s, z0.h, z0.h + movprfx z31, z15 + fmmla z31.s, z0.h, z30.h + movprfx z31, z15 + fmmla z31.s, z30.h, z0.h + movprfx z31, z15 + fmmla z31.s, z30.h, z30.h diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index b23fc7c6bc5..fd972fe1c05 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3198,16 +3198,16 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } -#define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } +#define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } #define F8F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } -#define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } +#define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \ + { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } #define F8F16MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F16MM, OPS, QUALS, FLAGS, 0, 0, NULL } -#define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } +#define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \ + { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } @@ -3274,11 +3274,11 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } -#define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SVE_BFSCALE_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } -#define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ +#define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \ CONSTRAINTS, TIED, NULL } #define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -6665,7 +6665,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_F64F64_INSN ("fmls", 0xc1d08010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0), /* SVE_BFSCALE instructions. */ - SVE_BFSCALE_INSN ("bfscale", 0x65098000, 0xffffe000, sve_misc, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, 2), + SVE_BFSCALE_INSN ("bfscale", 0x65098000, 0xffffe000, sve_misc, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2), SVE_BFSCALE_SME2_INSN ("bfscale", 0xc120a180, 0xfff0ffe1, sme_misc, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_H, 0, 1), SVE_BFSCALE_SME2_INSN ("bfscale", 0xc120a980, 0xfff0ffe3, sme_misc, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_H, 0, 1), SVE_BFSCALE_SME2_INSN ("bfscale", 0xc120b180, 0xffe1ffe1, sme_misc, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_H, 0, 1), @@ -6876,13 +6876,13 @@ const struct aarch64_opcode aarch64_opcode_table[] = BFLOAT16_INSN ("bfmlalb", 0x0fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0), /* SVE_F16F32 Matrix Multiply-Accumulate. */ - SVE_F16F32MM_INSN ("fmmla", 0x6420e400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0), + SVE_F16F32MM_INSN ("fmmla", 0x6420e400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX), /* F8F32 Matrix Multiply-Accumulate. */ F8F32MM_INSN ("fmmla", 0x6e80ec00, 0xffe0fc00, asimdmisc, 0, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), - F8F32MM_SVE2_INSN ("fmmla", 0x6420e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0), + F8F32MM_SVE2_INSN ("fmmla", 0x6420e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX), /* F8F16 Matrix Multiply-Accumulate. */ F8F16MM_INSN ("fmmla", 0x6e00ec00, 0xffe0fc00, asimdmisc, 0, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), - F8F16MM_SVE2_INSN ("fmmla", 0x6460e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0), + F8F16MM_SVE2_INSN ("fmmla", 0x6460e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX), /* cpyfp cpyfprn cpyfpwn cpyfpn cpyfm cpyfmrn cpyfmwn cpyfmn