From: Rajan Vaja <rajan.vaja@xilinx.com>
Date: Fri, 15 Feb 2019 04:42:01 +0000 (-0800)
Subject: dts: xilinx: Update zynqmp dts
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=cf9adf55b2dca8bfd34e0b426e75c74bd1ab4629;p=thirdparty%2Fu-boot.git

dts: xilinx: Update zynqmp dts

Update zynqmp dts files to sync with upstream binding.

Below DT nodes are updated:
* Firmware
* Clock
* zynqmp-power
* Power domain
* Reset
* Pinctrl

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index dc881b609cb..121dfd375c0 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -11,25 +11,25 @@
 	fclk0: fclk0 {
 		status = "disabled";
 		compatible = "xlnx,fclk";
-		clocks = <&clk 71>;
+		clocks = <&zynqmp_clk 71>;
 	};
 
 	fclk1: fclk1 {
 		status = "disabled";
 		compatible = "xlnx,fclk";
-		clocks = <&clk 72>;
+		clocks = <&zynqmp_clk 72>;
 	};
 
 	fclk2: fclk2 {
 		status = "disabled";
 		compatible = "xlnx,fclk";
-		clocks = <&clk 73>;
+		clocks = <&zynqmp_clk 73>;
 	};
 
 	fclk3: fclk3 {
 		status = "disabled";
 		compatible = "xlnx,fclk";
-		clocks = <&clk 74>;
+		clocks = <&zynqmp_clk 74>;
 	};
 
 	pss_ref_clk: pss_ref_clk {
@@ -67,14 +67,6 @@
 		clock-frequency = <27000000>;
 	};
 
-	clk: clk {
-		u-boot,dm-pre-reloc;
-		#clock-cells = <1>;
-		compatible = "xlnx,zynqmp-clk";
-		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
-		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
-	};
-
 	dp_aclk: dp_aclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -83,222 +75,238 @@
 	};
 };
 
+&zynqmp_firmware {
+	zynqmp_clk: clock-controller {
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		compatible = "xlnx,zynqmp-clk";
+		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
+			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
+		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
+			      "aux_ref_clk", "gt_crx_ref_clk";
+	};
+};
+
 &can0 {
-	clocks = <&clk 63>, <&clk 31>;
+	clocks = <&zynqmp_clk 63>, <&zynqmp_clk 31>;
 };
 
 &can1 {
-	clocks = <&clk 64>, <&clk 31>;
+	clocks = <&zynqmp_clk 64>, <&zynqmp_clk 31>;
 };
 
 &cpu0 {
-	clocks = <&clk 10>;
+	clocks = <&zynqmp_clk 10>;
 };
 
 &fpd_dma_chan1 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &fpd_dma_chan2 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &fpd_dma_chan3 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &fpd_dma_chan4 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &fpd_dma_chan5 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &fpd_dma_chan6 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &fpd_dma_chan7 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &fpd_dma_chan8 {
-	clocks = <&clk 19>, <&clk 31>;
+	clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
 };
 
 &gpu {
-	clocks = <&clk 24>, <&clk 25>, <&clk 26>;
+	clocks = <&zynqmp_clk 24>, <&zynqmp_clk 25>, <&zynqmp_clk 26>;
 };
 
 &lpd_dma_chan1 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &lpd_dma_chan2 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &lpd_dma_chan3 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &lpd_dma_chan4 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &lpd_dma_chan5 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &lpd_dma_chan6 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &lpd_dma_chan7 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &lpd_dma_chan8 {
-	clocks = <&clk 68>, <&clk 31>;
+	clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;
 };
 
 &nand0 {
-	clocks = <&clk 60>, <&clk 31>;
+	clocks = <&zynqmp_clk 60>, <&zynqmp_clk 31>;
 };
 
 &gem0 {
-	clocks = <&clk 31>, <&clk 104>, <&clk 45>, <&clk 49>, <&clk 44>;
+	clocks = <&zynqmp_clk 31>, <&zynqmp_clk 104>, <&zynqmp_clk 45>,
+		 <&zynqmp_clk 49>, <&zynqmp_clk 44>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem1 {
-	clocks = <&clk 31>, <&clk 105>, <&clk 46>, <&clk 50>, <&clk 44>;
+	clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, <&zynqmp_clk 46>,
+		 <&zynqmp_clk 50>, <&zynqmp_clk 44>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem2 {
-	clocks = <&clk 31>, <&clk 106>, <&clk 47>, <&clk 51>, <&clk 44>;
+	clocks = <&zynqmp_clk 31>, <&zynqmp_clk 106>, <&zynqmp_clk 47>,
+		 <&zynqmp_clk 51>, <&zynqmp_clk 44>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem3 {
-	clocks = <&clk 31>, <&clk 107>, <&clk 48>, <&clk 52>, <&clk 44>;
+	clocks = <&zynqmp_clk 31>, <&zynqmp_clk 107>, <&zynqmp_clk 48>,
+		 <&zynqmp_clk 52>, <&zynqmp_clk 44>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gpio {
-	clocks = <&clk 31>;
+	clocks = <&zynqmp_clk 31>;
 };
 
 &i2c0 {
-	clocks = <&clk 61>;
+	clocks = <&zynqmp_clk 61>;
 };
 
 &i2c1 {
-	clocks = <&clk 62>;
+	clocks = <&zynqmp_clk 62>;
 };
 
 &perf_monitor_ocm {
-	clocks = <&clk 31>;
+	clocks = <&zynqmp_clk 31>;
 };
 
 &perf_monitor_ddr {
-	clocks = <&clk 28>;
+	clocks = <&zynqmp_clk 28>;
 };
 
 &perf_monitor_cci {
-	clocks = <&clk 28>;
+	clocks = <&zynqmp_clk 28>;
 };
 
 &perf_monitor_lpd {
-	clocks = <&clk 31>;
+	clocks = <&zynqmp_clk 31>;
 };
 
 &pcie {
-	clocks = <&clk 23>;
+	clocks = <&zynqmp_clk 23>;
 };
 
 &qspi {
-	clocks = <&clk 53>, <&clk 31>;
+	clocks = <&zynqmp_clk 53>, <&zynqmp_clk 31>;
 };
 
 &sata {
-	clocks = <&clk 22>;
+	clocks = <&zynqmp_clk 22>;
 };
 
 &sdhci0 {
-	clocks = <&clk 54>, <&clk 31>;
+	clocks = <&zynqmp_clk 54>, <&zynqmp_clk 31>;
 };
 
 &sdhci1 {
-	clocks = <&clk 55>, <&clk 31>;
+	clocks = <&zynqmp_clk 55>, <&zynqmp_clk 31>;
 };
 
 &spi0 {
-	clocks = <&clk 58>, <&clk 31>;
+	clocks = <&zynqmp_clk 58>, <&zynqmp_clk 31>;
 };
 
 &spi1 {
-	clocks = <&clk 59>, <&clk 31>;
+	clocks = <&zynqmp_clk 59>, <&zynqmp_clk 31>;
 };
 
 &ttc0 {
-	clocks = <&clk 31>;
+	clocks = <&zynqmp_clk 31>;
 };
 
 &ttc1 {
-	clocks = <&clk 31>;
+	clocks = <&zynqmp_clk 31>;
 };
 
 &ttc2 {
-	clocks = <&clk 31>;
+	clocks = <&zynqmp_clk 31>;
 };
 
 &ttc3 {
-	clocks = <&clk 31>;
+	clocks = <&zynqmp_clk 31>;
 };
 
 &uart0 {
-	clocks = <&clk 56>, <&clk 31>;
+	clocks = <&zynqmp_clk 56>, <&zynqmp_clk 31>;
 };
 
 &uart1 {
-	clocks = <&clk 57>, <&clk 31>;
+	clocks = <&zynqmp_clk 57>, <&zynqmp_clk 31>;
 };
 
 &usb0 {
-	clocks = <&clk 32>, <&clk 34>;
+	clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;
 };
 
 &usb1 {
-	clocks = <&clk 33>, <&clk 34>;
+	clocks = <&zynqmp_clk 33>, <&zynqmp_clk 34>;
 };
 
 &watchdog0 {
-	clocks = <&clk 75>;
+	clocks = <&zynqmp_clk 75>;
 };
 
 &lpd_watchdog {
-	clocks = <&clk 112>;
+	clocks = <&zynqmp_clk 112>;
 };
 
 &xilinx_ams {
-	clocks = <&clk 70>;
+	clocks = <&zynqmp_clk 70>;
 };
 
 &zynqmp_dpsub {
-	clocks = <&dp_aclk>, <&clk 17>, <&clk 16>;
+	clocks = <&dp_aclk>, <&zynqmp_clk 17>, <&zynqmp_clk 16>;
 };
 
 &xlnx_dpdma {
-	clocks = <&clk 20>;
+	clocks = <&zynqmp_clk 20>;
 };
 
 &zynqmp_dp_snd_codec0 {
-	clocks = <&clk 17>;
+	clocks = <&zynqmp_clk 17>;
 };
 
 &pcap {
-	clocks = <&clk 41>;
+	clocks = <&zynqmp_clk 41>;
 };
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index e7d305f2dfc..1a70b771db7 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -12,6 +12,8 @@
  * the License, or (at your option) any later version.
  */
 
+#include <dt-bindings/power/xlnx-zynqmp-power.h>
+
 / {
 	compatible = "xlnx,zynqmp";
 	#address-cells = <2>;
@@ -102,173 +104,25 @@
 		u-boot,dm-pre-reloc;
 	};
 
-	pinctrl0: pinctrl {
-		compatible = "xlnx,zynqmp-pinctrl";
-		status = "disabled";
-	};
-
-	power-domains {
-		compatible = "xlnx,zynqmp-genpd";
-
-		pd_usb0: pd-usb0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x16>;
-		};
-
-		pd_usb1: pd-usb1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x17>;
-		};
-
-		pd_sata: pd-sata {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x1c>;
-		};
-
-		pd_spi0: pd-spi0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x23>;
-		};
-
-		pd_spi1: pd-spi1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x24>;
-		};
-
-		pd_uart0: pd-uart0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x21>;
-		};
-
-		pd_uart1: pd-uart1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x22>;
-		};
-
-		pd_eth0: pd-eth0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x1d>;
-		};
-
-		pd_eth1: pd-eth1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x1e>;
-		};
-
-		pd_eth2: pd-eth2 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x1f>;
-		};
-
-		pd_eth3: pd-eth3 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x20>;
-		};
-
-		pd_i2c0: pd-i2c0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x25>;
-		};
-
-		pd_i2c1: pd-i2c1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x26>;
-		};
-
-		pd_dp: pd-dp {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x29>;
-		};
-
-		pd_gdma: pd-gdma {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x2a>;
-		};
-
-		pd_adma: pd-adma {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x2b>;
-		};
-
-		pd_ttc0: pd-ttc0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x18>;
-		};
-
-		pd_ttc1: pd-ttc1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x19>;
-		};
-
-		pd_ttc2: pd-ttc2 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x1a>;
-		};
-
-		pd_ttc3: pd-ttc3 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x1b>;
-		};
-
-		pd_sd0: pd-sd0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x27>;
-		};
-
-		pd_sd1: pd-sd1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x28>;
-		};
-
-		pd_nand: pd-nand {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x2c>;
-		};
-
-		pd_qspi: pd-qspi {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x2d>;
-		};
-
-		pd_gpio: pd-gpio {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x2e>;
-		};
-
-		pd_can0: pd-can0 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x2f>;
-		};
-
-		pd_can1: pd-can1 {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x30>;
-		};
-
-		pd_pcie: pd-pcie {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x3b>;
-		};
-
-		pd_gpu: pd-gpu {
-			#power-domain-cells = <0x0>;
-			pd-id = <0x3a 0x14 0x15>;
-		};
-	};
-
-	/* PMU1<->APU IPI mailbox controller */
-	ipi_mailbox_pmu1: mailbox@ff990400 {
+	zynqmp_ipi {
 		compatible = "xlnx,zynqmp-ipi-mailbox";
-		reg = <0x0 0xff9905c0 0x0 0x20>,
-		      <0x0 0xff9905e0 0x0 0x20>,
-		      <0x0 0xff990e80 0x0 0x20>,
-		      <0x0 0xff990ea0 0x0 0x20>;
-		reg-names = "local_request_region", "local_response_region",
-			    "remote_request_region", "remote_response_region";
-		#mbox-cells = <1>;
-		xlnx,ipi-ids = <0 4>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 35 4>;
+		xlnx,ipi-id = <0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ipi_mailbox_pmu1: mailbox@ff990400 {
+			reg = <0x0 0xff9905c0 0x0 0x20>,
+			      <0x0 0xff9905e0 0x0 0x20>,
+			      <0x0 0xff990e80 0x0 0x20>,
+			      <0x0 0xff990ea0 0x0 0x20>;
+			reg-names = "local_request_region", "local_response_region",
+				    "remote_request_region", "remote_response_region";
+			#mbox-cells = <1>;
+			xlnx,ipi-id = <4>;
+		};
 	};
 
 	pmu {
@@ -289,14 +143,28 @@
 		zynqmp_firmware: zynqmp-firmware {
 			compatible = "xlnx,zynqmp-firmware";
 			method = "smc";
-		};
-	};
+			#power-domain-cells = <0x1>;
+			u-boot,dm-pre-reloc;
 
-	zynqmp_power: zynqmp-power {
-		compatible = "xlnx,zynqmp-power";
-		mboxes = <&ipi_mailbox_pmu1 0>,
-			 <&ipi_mailbox_pmu1 1>;
-		mbox-names = "tx", "rx";
+			zynqmp_power: zynqmp-power {
+				compatible = "xlnx,zynqmp-power";
+				interrupt-parent = <&gic>;
+				interrupts = <0 35 4>;
+				mboxes = <&ipi_mailbox_pmu1 0>,
+					 <&ipi_mailbox_pmu1 1>;
+				mbox-names = "tx", "rx";
+			};
+
+			zynqmp_reset: reset-controller {
+				compatible = "xlnx,zynqmp-reset";
+				#reset-cells = <1>;
+			};
+
+			pinctrl0: pinctrl {
+				compatible = "xlnx,zynqmp-pinctrl";
+				status = "disabled";
+			};
+		};
 	};
 
 	timer {
@@ -383,11 +251,6 @@
 		clock-names = "ref_clk";
 	};
 
-	rst: reset-controller {
-		compatible = "xlnx,zynqmp-reset";
-		#reset-cells = <1>;
-	};
-
 	xlnx_rsa: zynqmp_rsa {
 		compatible = "xlnx,zynqmp-rsa";
 	};
@@ -449,7 +312,7 @@
 			interrupt-parent = <&gic>;
 			tx-fifo-depth = <0x40>;
 			rx-fifo-depth = <0x40>;
-			power-domains = <&pd_can0>;
+			power-domains = <&zynqmp_firmware PD_CAN_0>;
 		};
 
 		can1: can@ff070000 {
@@ -461,7 +324,7 @@
 			interrupt-parent = <&gic>;
 			tx-fifo-depth = <0x40>;
 			rx-fifo-depth = <0x40>;
-			power-domains = <&pd_can1>;
+			power-domains = <&zynqmp_firmware PD_CAN_1>;
 		};
 
 		cci: cci@fd6e0000 {
@@ -494,7 +357,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14e8>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		fpd_dma_chan2: dma@fd510000 {
@@ -507,7 +370,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14e9>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		fpd_dma_chan3: dma@fd520000 {
@@ -520,7 +383,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14ea>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		fpd_dma_chan4: dma@fd530000 {
@@ -533,7 +396,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14eb>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		fpd_dma_chan5: dma@fd540000 {
@@ -546,7 +409,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14ec>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		fpd_dma_chan6: dma@fd550000 {
@@ -559,7 +422,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14ed>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		fpd_dma_chan7: dma@fd560000 {
@@ -572,7 +435,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14ee>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		fpd_dma_chan8: dma@fd570000 {
@@ -585,7 +448,7 @@
 			xlnx,bus-width = <128>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x14ef>;
-			power-domains = <&pd_gdma>;
+			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};
 
 		gpu: gpu@fd4b0000 {
@@ -596,7 +459,7 @@
 			interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 			clock-names = "gpu", "gpu_pp0", "gpu_pp1";
-			power-domains = <&pd_gpu>;
+			power-domains = <&zynqmp_firmware PD_GPU>;
 		};
 
 		/* LPDDMA default allows only secured access. inorder to enable
@@ -613,7 +476,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x868>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		lpd_dma_chan2: dma@ffa90000 {
@@ -626,7 +489,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x869>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		lpd_dma_chan3: dma@ffaa0000 {
@@ -639,7 +502,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x86a>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		lpd_dma_chan4: dma@ffab0000 {
@@ -652,7 +515,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x86b>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		lpd_dma_chan5: dma@ffac0000 {
@@ -665,7 +528,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x86c>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		lpd_dma_chan6: dma@ffad0000 {
@@ -678,7 +541,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x86d>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		lpd_dma_chan7: dma@ffae0000 {
@@ -691,7 +554,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x86e>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		lpd_dma_chan8: dma@ffaf0000 {
@@ -704,7 +567,7 @@
 			xlnx,bus-width = <64>;
 			#stream-id-cells = <1>;
 			/* iommus = <&smmu 0x86f>; */
-			power-domains = <&pd_adma>;
+			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};
 
 		mc: memory-controller@fd070000 {
@@ -725,7 +588,7 @@
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x872>;
-			power-domains = <&pd_nand>;
+			power-domains = <&zynqmp_firmware PD_NAND>;
 		};
 
 		gem0: ethernet@ff0b0000 {
@@ -739,7 +602,7 @@
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x874>;
-			power-domains = <&pd_eth0>;
+			power-domains = <&zynqmp_firmware PD_ETH_0>;
 		};
 
 		gem1: ethernet@ff0c0000 {
@@ -753,7 +616,7 @@
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x875>;
-			power-domains = <&pd_eth1>;
+			power-domains = <&zynqmp_firmware PD_ETH_1>;
 		};
 
 		gem2: ethernet@ff0d0000 {
@@ -767,7 +630,7 @@
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x876>;
-			power-domains = <&pd_eth2>;
+			power-domains = <&zynqmp_firmware PD_ETH_2>;
 		};
 
 		gem3: ethernet@ff0e0000 {
@@ -781,7 +644,7 @@
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x877>;
-			power-domains = <&pd_eth3>;
+			power-domains = <&zynqmp_firmware PD_ETH_3>;
 		};
 
 		gpio: gpio@ff0a0000 {
@@ -794,7 +657,7 @@
 			#interrupt-cells = <2>;
 			reg = <0x0 0xff0a0000 0x0 0x1000>;
 			gpio-controller;
-			power-domains = <&pd_gpio>;
+			power-domains = <&zynqmp_firmware PD_GPIO>;
 		};
 
 		i2c0: i2c@ff020000 {
@@ -805,7 +668,7 @@
 			reg = <0x0 0xff020000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			power-domains = <&pd_i2c0>;
+			power-domains = <&zynqmp_firmware PD_I2C_0>;
 		};
 
 		i2c1: i2c@ff030000 {
@@ -816,7 +679,7 @@
 			reg = <0x0 0xff030000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			power-domains = <&pd_i2c1>;
+			power-domains = <&zynqmp_firmware PD_I2C_1>;
 		};
 
 		ocm: memory-controller@ff960000 {
@@ -847,7 +710,7 @@
 		perf_monitor_ddr: perf-monitor@fd0b0000 {
 			compatible = "xlnx,axi-perf-monitor";
 			reg = <0x0 0xfd0b0000 0x0 0x10000>;
-			interrupts = <0 27 4>;
+			interrupts = <0 123 4>;
 			interrupt-parent = <&gic>;
 			xlnx,enable-profile = <0>;
 			xlnx,enable-trace = <0>;
@@ -865,7 +728,7 @@
 		perf_monitor_cci: perf-monitor@fd490000 {
 			compatible = "xlnx,axi-perf-monitor";
 			reg = <0x0 0xfd490000 0x0 0x10000>;
-			interrupts = <0 27 4>;
+			interrupts = <0 123 4>;
 			interrupt-parent = <&gic>;
 			xlnx,enable-profile = <0>;
 			xlnx,enable-trace = <0>;
@@ -927,7 +790,7 @@
 					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
-			power-domains = <&pd_pcie>;
+			power-domains = <&zynqmp_firmware PD_PCIE>;
 			pcie_intc: legacy-interrupt-controller {
 				interrupt-controller;
 				#address-cells = <0>;
@@ -949,7 +812,7 @@
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x873>;
-			power-domains = <&pd_qspi>;
+			power-domains = <&zynqmp_firmware PD_QSPI>;
 		};
 
 		rtc: rtc@ffa60000 {
@@ -970,10 +833,12 @@
 			reg-names = "serdes", "siou";
 			nvmem-cells = <&soc_revision>;
 			nvmem-cell-names = "soc_revision";
-			resets = <&rst 16>, <&rst 59>, <&rst 60>,
-				 <&rst 61>, <&rst 62>, <&rst 63>,
-				 <&rst 64>, <&rst 3>, <&rst 29>,
-				 <&rst 30>, <&rst 31>, <&rst 32>;
+			resets = <&zynqmp_reset 16>, <&zynqmp_reset 59>,
+				 <&zynqmp_reset 60>, <&zynqmp_reset 61>,
+				 <&zynqmp_reset 62>, <&zynqmp_reset 63>,
+				 <&zynqmp_reset 64>, <&zynqmp_reset 3>,
+				 <&zynqmp_reset 29>, <&zynqmp_reset 30>,
+				 <&zynqmp_reset 31>, <&zynqmp_reset 32>;
 			reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 				      "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 				      "usb1_apbrst", "dp_rst", "gem0_rst",
@@ -998,7 +863,7 @@
 			reg = <0x0 0xfd0c0000 0x0 0x2000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 133 4>;
-			power-domains = <&pd_sata>;
+			power-domains = <&zynqmp_firmware PD_SATA>;
 			#stream-id-cells = <4>;
 			/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, */
 			/*	 <&smmu 0x4c2>, <&smmu 0x4c3>; */
@@ -1016,7 +881,7 @@
 			xlnx,device_id = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x870>;
-			power-domains = <&pd_sd0>;
+			power-domains = <&zynqmp_firmware PD_SD_0>;
 			nvmem-cells = <&soc_revision>;
 			nvmem-cell-names = "soc_revision";
 		};
@@ -1032,7 +897,7 @@
 			xlnx,device_id = <1>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x871>;
-			power-domains = <&pd_sd1>;
+			power-domains = <&zynqmp_firmware PD_SD_1>;
 			nvmem-cells = <&soc_revision>;
 			nvmem-cell-names = "soc_revision";
 		};
@@ -1046,7 +911,7 @@
 			clock-names = "ref_clk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			power-domains = <&pd_spi0>;
+			power-domains = <&zynqmp_firmware PD_SPI_0>;
 		};
 
 		spi1: spi@ff050000 {
@@ -1058,7 +923,7 @@
 			clock-names = "ref_clk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			power-domains = <&pd_spi1>;
+			power-domains = <&zynqmp_firmware PD_SPI_1>;
 		};
 
 		ttc0: timer@ff110000 {
@@ -1068,7 +933,7 @@
 			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 			reg = <0x0 0xff110000 0x0 0x1000>;
 			timer-width = <32>;
-			power-domains = <&pd_ttc0>;
+			power-domains = <&zynqmp_firmware PD_TTC_0>;
 		};
 
 		ttc1: timer@ff120000 {
@@ -1078,7 +943,7 @@
 			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 			reg = <0x0 0xff120000 0x0 0x1000>;
 			timer-width = <32>;
-			power-domains = <&pd_ttc1>;
+			power-domains = <&zynqmp_firmware PD_TTC_1>;
 		};
 
 		ttc2: timer@ff130000 {
@@ -1088,7 +953,7 @@
 			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 			reg = <0x0 0xff130000 0x0 0x1000>;
 			timer-width = <32>;
-			power-domains = <&pd_ttc2>;
+			power-domains = <&zynqmp_firmware PD_TTC_2>;
 		};
 
 		ttc3: timer@ff140000 {
@@ -1098,7 +963,7 @@
 			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 			reg = <0x0 0xff140000 0x0 0x1000>;
 			timer-width = <32>;
-			power-domains = <&pd_ttc3>;
+			power-domains = <&zynqmp_firmware PD_TTC_3>;
 		};
 
 		uart0: serial@ff000000 {
@@ -1109,7 +974,7 @@
 			interrupts = <0 21 4>;
 			reg = <0x0 0xff000000 0x0 0x1000>;
 			clock-names = "uart_clk", "pclk";
-			power-domains = <&pd_uart0>;
+			power-domains = <&zynqmp_firmware PD_UART_0>;
 		};
 
 		uart1: serial@ff010000 {
@@ -1120,7 +985,7 @@
 			interrupts = <0 22 4>;
 			reg = <0x0 0xff010000 0x0 0x1000>;
 			clock-names = "uart_clk", "pclk";
-			power-domains = <&pd_uart1>;
+			power-domains = <&zynqmp_firmware PD_UART_1>;
 		};
 
 		usb0: usb0@ff9d0000 {
@@ -1130,7 +995,7 @@
 			compatible = "xlnx,zynqmp-dwc3";
 			reg = <0x0 0xff9d0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
-			power-domains = <&pd_usb0>;
+			power-domains = <&zynqmp_firmware PD_USB_0>;
 			ranges;
 			nvmem-cells = <&soc_revision>;
 			nvmem-cell-names = "soc_revision";
@@ -1160,7 +1025,7 @@
 			compatible = "xlnx,zynqmp-dwc3";
 			reg = <0x0 0xff9e0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
-			power-domains = <&pd_usb1>;
+			power-domains = <&zynqmp_firmware PD_USB_1>;
 			ranges;
 			nvmem-cells = <&soc_revision>;
 			nvmem-cell-names = "soc_revision";
@@ -1234,7 +1099,7 @@
 			interrupts = <0 122 4>;
 			interrupt-parent = <&gic>;
 			clock-names = "axi_clk";
-			power-domains = <&pd_dp>;
+			power-domains = <&zynqmp_firmware PD_DP>;
 			dma-channels = <6>;
 			#dma-cells = <1>;
 			dma-video0channel {
@@ -1271,7 +1136,7 @@
 			clock-names = "dp_apb_clk", "dp_aud_clk",
 				      "dp_vtc_pixel_clk_in";
 
-			power-domains = <&pd_dp>;
+			power-domains = <&zynqmp_firmware PD_DP>;
 
 			vid-layer {
 				dma-names = "vid0", "vid1", "vid2";