From: Eric Anholt <eric@anholt.net>
Date: Thu, 19 Jan 2012 18:50:06 +0000 (-0800)
Subject: drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.
X-Git-Tag: v3.2.38~40
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d31349bd14461e299df2443dfec5bf7725154393;p=thirdparty%2Fkernel%2Fstable.git

drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

commit fc74d8e01165b567922921d110b6d16320a61fa6 upstream.

Older specs claimed this was bit 11, but newer specs and the actual
simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
or try to enable it any more.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Anyone trying to use this bit, please read all the relevant
discussions, it's epic.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7a10f5fed1fb5..56d931ae28ad1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -399,7 +399,7 @@
 
 #define MI_MODE		0x0209c
 # define VS_TIMER_DISPATCH				(1 << 6)
-# define MI_FLUSH_ENABLE				(1 << 11)
+# define MI_FLUSH_ENABLE				(1 << 12)
 
 #define GEN6_GT_MODE	0x20d0
 #define   GEN6_GT_MODE_HI	(1 << 9)