From: Andrew Stubbs <ams@baylibre.com>
Date: Thu, 9 Jul 2026 16:27:54 +0000 (+0000)
Subject: amdgcn: Testsuite cond_fmaxnm fixups
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d338c42d76fa7ddec361fc344bf0c6add63c306b;p=thirdparty%2Fgcc.git

amdgcn: Testsuite cond_fmaxnm fixups

These testcases had a typo that means they scan for SFmode twice, and DFmode
never.  They were also incompatible with the pattern names in my address vector
patches (not yet committed).

This patch fixes both issues.

gcc/testsuite/ChangeLog:

	* gcc.target/gcn/cond_fmaxnm_3.c: Fix assembler scan patterns.
	* gcc.target/gcn/cond_fmaxnm_4.c: Fix assembler scan patterns.
	* gcc.target/gcn/cond_fminnm_3.c: Fix assembler scan patterns.
	* gcc.target/gcn/cond_fminnm_4.c: Fix assembler scan patterns.
---

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
index 5da33ac2726..0f1fcfbb149 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
@@ -30,8 +30,8 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
index 263db35dd49..7885808bca3 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
@@ -30,8 +30,8 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
index 59bbc5610ce..45b63c08814 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
@@ -7,8 +7,8 @@
 #include "cond_fmaxnm_3.c"
 
 /* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
index 07e6aae8919..bf41cc615a3 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
@@ -7,8 +7,8 @@
 #include "cond_fmaxnm_4.c"
 
 /* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */