From: SillyZ <1357816113@qq.com> Date: Tue, 16 Sep 2025 08:10:09 +0000 (+0800) Subject: hw/net/can: Remove redundant status bit setting in can_sja1000 X-Git-Tag: v10.2.0-rc1~79^2~6 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d56a30a7bba66de1b796af775928f77da25ca89b;p=thirdparty%2Fqemu.git hw/net/can: Remove redundant status bit setting in can_sja1000 In PeliCAN mode reception, the RBS (Receive Buffer Status) bit is set twice at line 842 and 845 with identical operations: s->status_pel |= 0x01; s->status_pel |= (1 << 0); Between these two operations, only interrupt_pel is modified and status_pel bit 4 is cleared, neither affecting bit 0. The second operation is redundant. This cleanup aligns PeliCAN mode with BasicCAN mode, which correctly sets this bit only once (line 883). Signed-off-by: SillyZ <1357816113@qq.com> Reviewed-by: Peter Maydell Reviewed-by: Michael Tokarev Signed-off-by: Michael Tokarev --- diff --git a/hw/net/can/can_sja1000.c b/hw/net/can/can_sja1000.c index 5b6ba9df6c..6b08e977a1 100644 --- a/hw/net/can/can_sja1000.c +++ b/hw/net/can/can_sja1000.c @@ -842,7 +842,6 @@ ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames, s->status_pel |= 0x01; /* Set the Receive Buffer Status. DS-p23 */ s->interrupt_pel |= 0x01; s->status_pel &= ~(1 << 4); - s->status_pel |= (1 << 0); can_sja_update_pel_irq(s); } else { /* BasicCAN mode */