From: Kathiravan Thirumoorthy Date: Tue, 12 Aug 2025 10:32:41 +0000 (+0530) Subject: arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE X-Git-Tag: v6.18-rc1~147^2~32^2~112 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d56ddcee0101a4b948be0d388e91f5f38f14d448;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the first SE, which supports a 4-wire UART configuration suitable for applications such as HS-UART. Note that the required initialization for this SE is not handled by the bootloader. Therefore, add the SE node in the device tree but keep it reserved. Enable it once Linux gains support for configuring the SE, allowing to use in relevant RDPs. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250812-ipq5424_hsuart-v4-1-f1faa7704ea9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 117f1785e8b8e..738618551203b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -224,6 +224,13 @@ }; }; + uart0_pins: uart0-default-state { + pins = "gpio10", "gpio11", "gpio12", "gpio13"; + function = "uart0"; + drive-strength = <8>; + bias-pull-down; + }; + pcie2_default_state: pcie2-default-state { pins = "gpio31"; function = "gpio"; @@ -239,6 +246,17 @@ }; }; +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + /* + * The required initialization for this SE is not handled by the + * bootloader. Therefore, keep the device in "reserved" state until + * linux gains support for configuring the SE. + */ + status = "reserved"; +}; + &uart1 { pinctrl-0 = <&uart1_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 2eea8a0785951..bd891e39f33e1 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -442,6 +442,15 @@ #address-cells = <2>; #size-cells = <2>; + uart0: serial@1a80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x01a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_UART0_CLK>; + clock-names = "se"; + interrupts = ; + status = "disabled"; + }; + uart1: serial@1a84000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x01a84000 0 0x4000>;