From: Jakub Kicinski Date: Sat, 28 Feb 2026 18:30:26 +0000 (-0800) Subject: Merge branch 'npc-hw-block-support-for-cn20k' X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d578b4729399979f14f7ddd6a80e3ae0832c2e0c;p=thirdparty%2Fkernel%2Flinux.git Merge branch 'npc-hw-block-support-for-cn20k' Ratheesh Kannoth says: ==================== NPC HW block support for cn20k This patchset adds comprehensive support for the CN20K NPC architecture. CN20K introduces significant changes in MCAM layout, parser design, KPM/KPU mapping, index management, virtual index handling, and dynamic rule installation. The patches update the AF, PF/VF, and common layers to correctly support these new capabilities while preserving compatibility with previous silicon variants. MCAM on CN20K differs from older designs: the hardware now contains two vertical banks of depth 8192, and thirty-two horizontal subbanks of depth 256. Each subbank can be configured as x2 or x4, enabling 256-bit or 512-bit key storage. Several allocation models are added to support this layout, including contiguous and non-contiguous allocation with or without reference ranges and priorities. Parser and extraction logic are also enhanced. CN20K introduces a new profile model where up to twenty-four extractors may be configured for each parsing profile. A new KPM profile scheme is added, grouping sixteen KPUs into eight KPM profiles, each formed by two KPUs. Support is added for default index allocation for CN20K-specific MCAM entry structures, virtual index allocation, improved defragmentation, and TC rule installation by allowing the AF driver to determine required x2/x4 rule width during flow install. ==================== Link: https://patch.msgid.link/20260224080009.4147301-1-rkannoth@marvell.com Signed-off-by: Jakub Kicinski --- d578b4729399979f14f7ddd6a80e3ae0832c2e0c