From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
Date: Tue, 11 Feb 2014 01:52:54 +0000 (+0000)
Subject: Added the lwr/swr instructions pattern.
X-Git-Tag: releases/gcc-4.9.0~969
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d63f13116fae7379c1645582bdc6c2e7c02cd56c;p=thirdparty%2Fgcc.git

Added the lwr/swr instructions pattern.

lwr and swr instructions will load/store the data with opposite endianness.

Changelog

2014-02-10  Nagaraju Mekala <nagaraju.mekala@xilinx.com>

 * gcc/config/microblaze/microblaze.md: Add movsi4_rev insn pattern.
 * gcc/config/microblaze/predicates.md: Add reg_or_mem_operand predicate.

From-SVN: r207683
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8198a5f3b515..1a61595cd8c6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,4 +1,9 @@
-2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+2014-02-10  Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+	* config/microblaze/microblaze.md: Add movsi4_rev insn pattern.
+	* config/microblaze/predicates.md: Add reg_or_mem_operand predicate.
+
+2014-02-10  Nagaraju Mekala <nagaraju.mekala@xilinx.com>
 
 	* config/microblaze/microblaze.c: Extend mcpu version format
 
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 8431f2de3abf..01c49e002799 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -1119,6 +1119,18 @@
   }
 )
 
+;;Load and store reverse
+(define_insn "movsi4_rev"
+  [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Q")
+        (bswap:SI (match_operand:SF 1 "reg_or_mem_operand" "Q,r")))]
+  "TARGET_REORDER"
+  "@
+   lwr\t%0,%y1,r0
+   swr\t%1,%y0,r0"
+  [(set_attr "type"     "load,store")
+  (set_attr "mode"      "SI")
+  (set_attr "length"    "4,4")])
+
 ;; 32-bit floating point moves
 
 (define_expand "movsf"
diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
index 83e8e79ac46f..f34453ca8eef 100644
--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
@@ -85,6 +85,10 @@
   (ior (match_operand 0 "const_0_operand")
        (match_operand 0 "register_operand")))
 
+(define_predicate "reg_or_mem_operand"
+  (ior (match_operand 0 "memory_operand")
+       (match_operand 0 "register_operand")))
+
 ;;  Return if the operand is either the PC or a label_ref.  
 (define_special_predicate "pc_or_label_operand"
   (ior (match_code "pc,label_ref")