From: Wadim Egorov Date: Wed, 21 May 2025 05:33:39 +0000 (+0200) Subject: arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports X-Git-Tag: v6.16.1~568 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d6788344cd5ef2f521e868ae282ad190a24dde2e;p=thirdparty%2Fkernel%2Fstable.git arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports [ Upstream commit 945e48a39c957924bc84d1a6c137da039e13855b ] For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must be supplied on CLKOUT0. Previously, our bootloader configured this clock, which is why the PRU Ethernet ports appeared to work, but the change never made it into the device tree. Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock. Signed-off-by: Wadim Egorov Fixes: 87adfd1ab03a ("arm64: dts: ti: am642-phyboard-electra: Add PRU-ICSSG nodes") Link: https://lore.kernel.org/r/20250521053339.1751844-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra Signed-off-by: Sasha Levin --- diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index f63c101b7d61a..129524eb5b912 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -322,6 +322,8 @@ &icssg0_mdio { pinctrl-names = "default"; pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>; + assigned-clocks = <&k3_clks 157 123>; + assigned-clock-parents = <&k3_clks 157 125>; status = "okay"; icssg0_phy1: ethernet-phy@1 {