From: Val Packett Date: Thu, 5 Dec 2024 18:29:36 +0000 (-0300) Subject: clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066 X-Git-Tag: v6.15-rc1~103^2~1^2~1^2~8 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=d7169b8bcd855828cc691baee5e778af96855573;p=thirdparty%2Fkernel%2Flinux.git clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066 RK3066 has two "CIF" video capture interface blocks, reference the newly added IDs for their PCLK clocks. Signed-off-by: Val Packett Link: https://lore.kernel.org/r/20241205182954.5346-2-val@packett.cool Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 30e670c8afbae..318c8ddc8a76c 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -337,7 +337,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(0, "pclkin_cif0", "ext_cif0", 0, RK2928_CLKGATE_CON(3), 3, GFLAGS), - INVERTER(0, "pclk_cif0", "pclkin_cif0", + INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0", RK2928_CLKSEL_CON(30), 8, IFLAGS), FACTOR(0, "xin12m", "xin24m", 0, 1, 2), @@ -595,7 +595,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(0, "pclkin_cif1", "ext_cif1", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), - INVERTER(0, "pclk_cif1", "pclkin_cif1", + INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1", RK2928_CLKSEL_CON(30), 12, IFLAGS), COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,