From: Greg Kroah-Hartman Date: Wed, 9 Aug 2023 09:07:26 +0000 (+0200) Subject: 6.1-stable patches X-Git-Tag: v4.14.322~14 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=db72a957246f32b8b8b76650a55209971200a9f5;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: arm64-ptrace-don-t-enable-sve-when-setting-streaming-sve.patch drm-amd-display-ensure-that-planes-are-in-the-same-order.patch drm-amd-display-skip-clear_payload_id_table-if-device-mst_en-is-0.patch --- diff --git a/queue-6.1/arm64-fpsimd-track-the-saved-fpsimd-state-type-separ.patch b/queue-6.1/arm64-fpsimd-track-the-saved-fpsimd-state-type-separ.patch deleted file mode 100644 index 26506d09005..00000000000 --- a/queue-6.1/arm64-fpsimd-track-the-saved-fpsimd-state-type-separ.patch +++ /dev/null @@ -1,361 +0,0 @@ -From 2867ca5ed28c178877ffdbb3987450491c8d61ce Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 15 Nov 2022 09:46:34 +0000 -Subject: arm64/fpsimd: Track the saved FPSIMD state type separately to TIF_SVE - -From: Mark Brown - -[ Upstream commit baa8515281b30861cff3da7db70662d2a25c6440 ] - -When we save the state for the floating point registers this can be done -in the form visible through either the FPSIMD V registers or the SVE Z and -P registers. At present we track which format is currently used based on -TIF_SVE and the SME streaming mode state but particularly in the SVE case -this limits our options for optimising things, especially around syscalls. -Introduce a new enum which we place together with saved floating point -state in both thread_struct and the KVM guest state which explicitly -states which format is active and keep it up to date when we change it. - -At present we do not use this state except to verify that it has the -expected value when loading the state, future patches will introduce -functional changes. - -Signed-off-by: Mark Brown -Reviewed-by: Catalin Marinas -Reviewed-by: Marc Zyngier -Link: https://lore.kernel.org/r/20221115094640.112848-3-broonie@kernel.org -Signed-off-by: Will Deacon -Stable-dep-of: 045aecdfcb2e ("arm64/ptrace: Don't enable SVE when setting streaming SVE") -Signed-off-by: Sasha Levin ---- - arch/arm64/include/asm/fpsimd.h | 2 +- - arch/arm64/include/asm/kvm_host.h | 12 ++++++- - arch/arm64/include/asm/processor.h | 6 ++++ - arch/arm64/kernel/fpsimd.c | 58 ++++++++++++++++++++++-------- - arch/arm64/kernel/process.c | 2 ++ - arch/arm64/kernel/ptrace.c | 3 ++ - arch/arm64/kernel/signal.c | 7 +++- - arch/arm64/kvm/fpsimd.c | 3 +- - 8 files changed, 74 insertions(+), 19 deletions(-) - -diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h -index c07e4abaca3d6..341705fcb7bb6 100644 ---- a/arch/arm64/include/asm/fpsimd.h -+++ b/arch/arm64/include/asm/fpsimd.h -@@ -61,7 +61,7 @@ extern void fpsimd_kvm_prepare(void); - extern void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *state, - void *sve_state, unsigned int sve_vl, - void *za_state, unsigned int sme_vl, -- u64 *svcr); -+ u64 *svcr, enum fp_type *type); - - extern void fpsimd_flush_task_state(struct task_struct *target); - extern void fpsimd_save_and_flush_cpu_state(void); -diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h -index b5a8e8b3c691c..153e3dcc98c26 100644 ---- a/arch/arm64/include/asm/kvm_host.h -+++ b/arch/arm64/include/asm/kvm_host.h -@@ -309,8 +309,18 @@ struct vcpu_reset_state { - struct kvm_vcpu_arch { - struct kvm_cpu_context ctxt; - -- /* Guest floating point state */ -+ /* -+ * Guest floating point state -+ * -+ * The architecture has two main floating point extensions, -+ * the original FPSIMD and SVE. These have overlapping -+ * register views, with the FPSIMD V registers occupying the -+ * low 128 bits of the SVE Z registers. When the core -+ * floating point code saves the register state of a task it -+ * records which view it saved in fp_type. -+ */ - void *sve_state; -+ enum fp_type fp_type; - unsigned int sve_max_vl; - u64 svcr; - -diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h -index 400f8956328b9..208434a2e9247 100644 ---- a/arch/arm64/include/asm/processor.h -+++ b/arch/arm64/include/asm/processor.h -@@ -122,6 +122,11 @@ enum vec_type { - ARM64_VEC_MAX, - }; - -+enum fp_type { -+ FP_STATE_FPSIMD, -+ FP_STATE_SVE, -+}; -+ - struct cpu_context { - unsigned long x19; - unsigned long x20; -@@ -152,6 +157,7 @@ struct thread_struct { - struct user_fpsimd_state fpsimd_state; - } uw; - -+ enum fp_type fp_type; /* registers FPSIMD or SVE? */ - unsigned int fpsimd_cpu; - void *sve_state; /* SVE registers, if any */ - void *za_state; /* ZA register, if any */ -diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c -index 63d796ad95411..af81a4a99b28e 100644 ---- a/arch/arm64/kernel/fpsimd.c -+++ b/arch/arm64/kernel/fpsimd.c -@@ -125,6 +125,7 @@ struct fpsimd_last_state_struct { - u64 *svcr; - unsigned int sve_vl; - unsigned int sme_vl; -+ enum fp_type *fp_type; - }; - - static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state); -@@ -330,15 +331,6 @@ void task_set_vl_onexec(struct task_struct *task, enum vec_type type, - * The task can execute SVE instructions while in userspace without - * trapping to the kernel. - * -- * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the -- * corresponding Zn), P0-P15 and FFR are encoded in -- * task->thread.sve_state, formatted appropriately for vector -- * length task->thread.sve_vl or, if SVCR.SM is set, -- * task->thread.sme_vl. -- * -- * task->thread.sve_state must point to a valid buffer at least -- * sve_state_size(task) bytes in size. -- * - * During any syscall, the kernel may optionally clear TIF_SVE and - * discard the vector state except for the FPSIMD subset. - * -@@ -348,7 +340,15 @@ void task_set_vl_onexec(struct task_struct *task, enum vec_type type, - * do_sve_acc() to be called, which does some preparation and then - * sets TIF_SVE. - * -- * When stored, FPSIMD registers V0-V31 are encoded in -+ * During any syscall, the kernel may optionally clear TIF_SVE and -+ * discard the vector state except for the FPSIMD subset. -+ * -+ * The data will be stored in one of two formats: -+ * -+ * * FPSIMD only - FP_STATE_FPSIMD: -+ * -+ * When the FPSIMD only state stored task->thread.fp_type is set to -+ * FP_STATE_FPSIMD, the FPSIMD registers V0-V31 are encoded in - * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are - * logically zero but not stored anywhere; P0-P15 and FFR are not - * stored and have unspecified values from userspace's point of -@@ -358,6 +358,19 @@ void task_set_vl_onexec(struct task_struct *task, enum vec_type type, - * task->thread.sve_state does not need to be non-NULL, valid or any - * particular size: it must not be dereferenced. - * -+ * * SVE state - FP_STATE_SVE: -+ * -+ * When the full SVE state is stored task->thread.fp_type is set to -+ * FP_STATE_SVE and Z0-Z31 (incorporating Vn in bits[127:0] or the -+ * corresponding Zn), P0-P15 and FFR are encoded in in -+ * task->thread.sve_state, formatted appropriately for vector -+ * length task->thread.sve_vl or, if SVCR.SM is set, -+ * task->thread.sme_vl. The storage for the vector registers in -+ * task->thread.uw.fpsimd_state should be ignored. -+ * -+ * task->thread.sve_state must point to a valid buffer at least -+ * sve_state_size(task) bytes in size. -+ * - * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state - * irrespective of whether TIF_SVE is clear or set, since these are - * not vector length dependent. -@@ -404,12 +417,15 @@ static void task_fpsimd_load(void) - } - } - -- if (restore_sve_regs) -+ if (restore_sve_regs) { -+ WARN_ON_ONCE(current->thread.fp_type != FP_STATE_SVE); - sve_load_state(sve_pffr(¤t->thread), - ¤t->thread.uw.fpsimd_state.fpsr, - restore_ffr); -- else -+ } else { -+ WARN_ON_ONCE(current->thread.fp_type != FP_STATE_FPSIMD); - fpsimd_load_state(¤t->thread.uw.fpsimd_state); -+ } - } - - /* -@@ -474,8 +490,10 @@ static void fpsimd_save(void) - sve_save_state((char *)last->sve_state + - sve_ffr_offset(vl), - &last->st->fpsr, save_ffr); -+ *last->fp_type = FP_STATE_SVE; - } else { - fpsimd_save_state(last->st); -+ *last->fp_type = FP_STATE_FPSIMD; - } - } - -@@ -851,8 +869,10 @@ int vec_set_vector_length(struct task_struct *task, enum vec_type type, - - fpsimd_flush_task_state(task); - if (test_and_clear_tsk_thread_flag(task, TIF_SVE) || -- thread_sm_enabled(&task->thread)) -+ thread_sm_enabled(&task->thread)) { - sve_to_fpsimd(task); -+ task->thread.fp_type = FP_STATE_FPSIMD; -+ } - - if (system_supports_sme()) { - if (type == ARM64_VEC_SME || -@@ -1386,6 +1406,7 @@ static void sve_init_regs(void) - fpsimd_bind_task_to_cpu(); - } else { - fpsimd_to_sve(current); -+ current->thread.fp_type = FP_STATE_SVE; - } - } - -@@ -1614,6 +1635,8 @@ void fpsimd_flush_thread(void) - current->thread.svcr = 0; - } - -+ current->thread.fp_type = FP_STATE_FPSIMD; -+ - put_cpu_fpsimd_context(); - kfree(sve_state); - kfree(za_state); -@@ -1662,8 +1685,10 @@ void fpsimd_kvm_prepare(void) - */ - get_cpu_fpsimd_context(); - -- if (test_and_clear_thread_flag(TIF_SVE)) -+ if (test_and_clear_thread_flag(TIF_SVE)) { - sve_to_fpsimd(current); -+ current->thread.fp_type = FP_STATE_FPSIMD; -+ } - - put_cpu_fpsimd_context(); - } -@@ -1685,6 +1710,7 @@ static void fpsimd_bind_task_to_cpu(void) - last->sve_vl = task_get_sve_vl(current); - last->sme_vl = task_get_sme_vl(current); - last->svcr = ¤t->thread.svcr; -+ last->fp_type = ¤t->thread.fp_type; - current->thread.fpsimd_cpu = smp_processor_id(); - - /* -@@ -1708,7 +1734,8 @@ static void fpsimd_bind_task_to_cpu(void) - - void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, - unsigned int sve_vl, void *za_state, -- unsigned int sme_vl, u64 *svcr) -+ unsigned int sme_vl, u64 *svcr, -+ enum fp_type *type) - { - struct fpsimd_last_state_struct *last = - this_cpu_ptr(&fpsimd_last_state); -@@ -1722,6 +1749,7 @@ void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, - last->za_state = za_state; - last->sve_vl = sve_vl; - last->sme_vl = sme_vl; -+ last->fp_type = type; - } - - /* -diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c -index 044a7d7f1f6ad..19cd05eea3f0e 100644 ---- a/arch/arm64/kernel/process.c -+++ b/arch/arm64/kernel/process.c -@@ -331,6 +331,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) - clear_tsk_thread_flag(dst, TIF_SME); - } - -+ dst->thread.fp_type = FP_STATE_FPSIMD; -+ - /* clear any pending asynchronous tag fault raised by the parent */ - clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT); - -diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c -index 92bc9a2d702cb..30e71a0b3955c 100644 ---- a/arch/arm64/kernel/ptrace.c -+++ b/arch/arm64/kernel/ptrace.c -@@ -909,6 +909,7 @@ static int sve_set_common(struct task_struct *target, - clear_tsk_thread_flag(target, TIF_SVE); - if (type == ARM64_VEC_SME) - fpsimd_force_sync_to_sve(target); -+ target->thread.fp_type = FP_STATE_FPSIMD; - goto out; - } - -@@ -931,6 +932,7 @@ static int sve_set_common(struct task_struct *target, - if (!target->thread.sve_state) { - ret = -ENOMEM; - clear_tsk_thread_flag(target, TIF_SVE); -+ target->thread.fp_type = FP_STATE_FPSIMD; - goto out; - } - -@@ -942,6 +944,7 @@ static int sve_set_common(struct task_struct *target, - */ - fpsimd_sync_to_sve(target); - set_tsk_thread_flag(target, TIF_SVE); -+ target->thread.fp_type = FP_STATE_SVE; - - BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); - start = SVE_PT_SVE_OFFSET; -diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c -index 43adbfa5ead78..be279fd482480 100644 ---- a/arch/arm64/kernel/signal.c -+++ b/arch/arm64/kernel/signal.c -@@ -207,6 +207,7 @@ static int restore_fpsimd_context(struct fpsimd_context __user *ctx) - __get_user_error(fpsimd.fpcr, &ctx->fpcr, err); - - clear_thread_flag(TIF_SVE); -+ current->thread.fp_type = FP_STATE_FPSIMD; - - /* load the hardware registers from the fpsimd_state structure */ - if (!err) -@@ -297,6 +298,7 @@ static int restore_sve_fpsimd_context(struct user_ctxs *user) - if (sve.head.size <= sizeof(*user->sve)) { - clear_thread_flag(TIF_SVE); - current->thread.svcr &= ~SVCR_SM_MASK; -+ current->thread.fp_type = FP_STATE_FPSIMD; - goto fpsimd_only; - } - -@@ -332,6 +334,7 @@ static int restore_sve_fpsimd_context(struct user_ctxs *user) - current->thread.svcr |= SVCR_SM_MASK; - else - set_thread_flag(TIF_SVE); -+ current->thread.fp_type = FP_STATE_SVE; - - fpsimd_only: - /* copy the FP and status/control registers */ -@@ -937,9 +940,11 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka, - * FPSIMD register state - flush the saved FPSIMD - * register state in case it gets loaded. - */ -- if (current->thread.svcr & SVCR_SM_MASK) -+ if (current->thread.svcr & SVCR_SM_MASK) { - memset(¤t->thread.uw.fpsimd_state, 0, - sizeof(current->thread.uw.fpsimd_state)); -+ current->thread.fp_type = FP_STATE_FPSIMD; -+ } - - current->thread.svcr &= ~(SVCR_ZA_MASK | - SVCR_SM_MASK); -diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c -index 51ca78b31b952..a4b4502ad850a 100644 ---- a/arch/arm64/kvm/fpsimd.c -+++ b/arch/arm64/kvm/fpsimd.c -@@ -140,7 +140,8 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) - fpsimd_bind_state_to_cpu(&vcpu->arch.ctxt.fp_regs, - vcpu->arch.sve_state, - vcpu->arch.sve_max_vl, -- NULL, 0, &vcpu->arch.svcr); -+ NULL, 0, &vcpu->arch.svcr, -+ &vcpu->arch.fp_type); - - clear_thread_flag(TIF_FOREIGN_FPSTATE); - update_thread_flag(TIF_SVE, vcpu_has_sve(vcpu)); --- -2.40.1 - diff --git a/queue-6.1/arm64-ptrace-don-t-enable-sve-when-setting-streaming.patch b/queue-6.1/arm64-ptrace-don-t-enable-sve-when-setting-streaming-sve.patch similarity index 81% rename from queue-6.1/arm64-ptrace-don-t-enable-sve-when-setting-streaming.patch rename to queue-6.1/arm64-ptrace-don-t-enable-sve-when-setting-streaming-sve.patch index 13d6014d407..fad86d04007 100644 --- a/queue-6.1/arm64-ptrace-don-t-enable-sve-when-setting-streaming.patch +++ b/queue-6.1/arm64-ptrace-don-t-enable-sve-when-setting-streaming-sve.patch @@ -1,11 +1,11 @@ -From 0bd1d67586c6015e6ea2b6e99230c195514a7a8e Mon Sep 17 00:00:00 2001 -From: Sasha Levin +From 045aecdfcb2e060db142d83a0f4082380c465d2c Mon Sep 17 00:00:00 2001 +From: Mark Brown Date: Thu, 3 Aug 2023 19:33:21 +0100 Subject: arm64/ptrace: Don't enable SVE when setting streaming SVE From: Mark Brown -[ Upstream commit 045aecdfcb2e060db142d83a0f4082380c465d2c ] +commit 045aecdfcb2e060db142d83a0f4082380c465d2c upstream. Systems which implement SME without also implementing SVE are architecturally valid but were not initially supported by the kernel, @@ -31,16 +31,16 @@ Signed-off-by: Mark Brown Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230803-arm64-fix-ptrace-ssve-no-sve-v1-1-49df214bfb3e@kernel.org Signed-off-by: Catalin Marinas -Signed-off-by: Sasha Levin +[Fix up backport -- broonie] +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman --- - arch/arm64/kernel/ptrace.c | 8 +++++--- + arch/arm64/kernel/ptrace.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c -index 30e71a0b3955c..5da65d235ce26 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c -@@ -939,11 +939,13 @@ static int sve_set_common(struct task_struct *target, +@@ -937,11 +937,13 @@ static int sve_set_common(struct task_st /* * Ensure target->thread.sve_state is up to date with target's * FPSIMD regs, so that a short copyin leaves trailing @@ -54,9 +54,6 @@ index 30e71a0b3955c..5da65d235ce26 100644 - set_tsk_thread_flag(target, TIF_SVE); + if (type == ARM64_VEC_SVE) + set_tsk_thread_flag(target, TIF_SVE); - target->thread.fp_type = FP_STATE_SVE; BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); --- -2.40.1 - + start = SVE_PT_SVE_OFFSET; diff --git a/queue-6.1/drm-amd-display-ensure-that-planes-are-in-the-same-order.patch b/queue-6.1/drm-amd-display-ensure-that-planes-are-in-the-same-order.patch new file mode 100644 index 00000000000..0f3af121190 --- /dev/null +++ b/queue-6.1/drm-amd-display-ensure-that-planes-are-in-the-same-order.patch @@ -0,0 +1,89 @@ +From bb46a6a9bab134b9d15043ea8fa9d6c276e938b8 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Thu, 16 Feb 2023 09:49:22 -0700 +Subject: drm/amd/display: Ensure that planes are in the same order + +From: Rodrigo Siqueira + +commit bb46a6a9bab134b9d15043ea8fa9d6c276e938b8 upstream. + +The function dc_update_planes_and_stream handles multiple cases where DC +needs to remove and add planes in the commit tail phase. After Linux +started to use this function, some of the IGT kms_plane started to fail; +one good example to illustrate why the new sequence regressed IGT is the +subtest plane-position-hole which has the following diagram as a +template: + + +--------------------+ +-----------------------+ + | +-----+ | | +-----+ | + | | | | | | +-----+ | + | | +--+ | ==> | | | | | | + | |__| | | +-|---+ | | + | | | +-----+ | + | | | | + +--------------------+ +-----------------------+ + (a) Final image (b) Composed image + +IGT expects image (a) as the final result of two plane compositions as +described in figure (b). After the migration to the new sequence, the +last plane order is changed, and DC generates the following image: + ++---------------------+ +| +-----+ | +| | | | +| | | | +| +-----+ | +| | ++---------------------+ + +Notice that the generated image by DC is different because the small +square that should be composed on top of the primary plane is below the +primary plane. For this reason, the CRC will mismatch with the expected +value. Since the function dc_add_all_planes_for_stream re-append all the +new planes back to the dc_validation_set, this commit ensures that the +original sequence is maintained. After this change, all CI tests in all +ASICs start to pass again. + +Reviewed-by: Harry Wentland +Acked-by: Qingqing Zhuo +Suggested-by: Melissa Wen +Signed-off-by: Rodrigo Siqueira +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Cc: Mario Limonciello +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -351,6 +351,19 @@ static inline bool is_dc_timing_adjust_n + return false; + } + ++static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, ++ int planes_count) ++{ ++ int i, j; ++ struct dc_surface_update surface_updates_temp; ++ ++ for (i = 0, j = planes_count - 1; i < j; i++, j--) { ++ surface_updates_temp = array_of_surface_update[i]; ++ array_of_surface_update[i] = array_of_surface_update[j]; ++ array_of_surface_update[j] = surface_updates_temp; ++ } ++} ++ + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * +@@ -367,6 +380,8 @@ static inline bool update_planes_and_str + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { ++ reverse_planes_order(array_of_surface_update, planes_count); ++ + /* + * Previous frame finished and HW is ready for optimization. + */ diff --git a/queue-6.1/drm-amd-display-skip-clear_payload_id_table-if-device-mst_en-is-0.patch b/queue-6.1/drm-amd-display-skip-clear_payload_id_table-if-device-mst_en-is-0.patch new file mode 100644 index 00000000000..66a5c1e4cba --- /dev/null +++ b/queue-6.1/drm-amd-display-skip-clear_payload_id_table-if-device-mst_en-is-0.patch @@ -0,0 +1,51 @@ +From a1c9a1e27022d13c70a14c4faeab6ce293ad043b Mon Sep 17 00:00:00 2001 +From: Peichen Huang +Date: Mon, 20 Mar 2023 09:34:23 +0800 +Subject: drm/amd/display: skip CLEAR_PAYLOAD_ID_TABLE if device mst_en is 0 + +From: Peichen Huang + +commit a1c9a1e27022d13c70a14c4faeab6ce293ad043b upstream. + +[Why] +Some dock and mst monitor don't like to receive CLEAR_PAYLOAD_ID_TABLE +when mst_en is set to 0. It doesn't make sense to do so in source +side, either. + +[How] +Don't send CLEAR_PAYLOAD_ID_TABLE if mst_en is 0 + +Reviewed-by: George Shen +Acked-by: Qingqing Zhuo +Signed-off-by: Peichen Huang +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +[ 6.1.y doesn't have the file rename from + 54618888d1ea7 ("drm/amd/display: break down dc_link.c") ] +Signed-off-by: Mario Limonciello +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -2092,6 +2092,7 @@ static enum dc_status enable_link_dp_mst + struct pipe_ctx *pipe_ctx) + { + struct dc_link *link = pipe_ctx->stream->link; ++ unsigned char mstm_cntl; + + /* sink signal type after MST branch is MST. Multiple MST sinks + * share one link. Link DP PHY is enable or training only once. +@@ -2100,7 +2101,9 @@ static enum dc_status enable_link_dp_mst + return DC_OK; + + /* clear payload table */ +- dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); ++ core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); ++ if (mstm_cntl & DP_MST_EN) ++ dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); + + /* to make sure the pending down rep can be processed + * before enabling the link diff --git a/queue-6.1/kvm-arm64-discard-any-sve-state-when-entering-kvm-gu.patch b/queue-6.1/kvm-arm64-discard-any-sve-state-when-entering-kvm-gu.patch deleted file mode 100644 index d6630f03ce8..00000000000 --- a/queue-6.1/kvm-arm64-discard-any-sve-state-when-entering-kvm-gu.patch +++ /dev/null @@ -1,99 +0,0 @@ -From d2617b724dd53b03ad06bce44b7d4d098244f403 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Tue, 15 Nov 2022 09:46:33 +0000 -Subject: KVM: arm64: Discard any SVE state when entering KVM guests - -From: Mark Brown - -[ Upstream commit 93ae6b01bafee8fa385aa25ee7ebdb40057f6abe ] - -Since 8383741ab2e773a99 (KVM: arm64: Get rid of host SVE tracking/saving) -KVM has not tracked the host SVE state, relying on the fact that we -currently disable SVE whenever we perform a syscall. This may not be true -in future since performance optimisation may result in us keeping SVE -enabled in order to avoid needing to take access traps to reenable it. -Handle this by clearing TIF_SVE and converting the stored task state to -FPSIMD format when preparing to run the guest. This is done with a new -call fpsimd_kvm_prepare() to keep the direct state manipulation -functions internal to fpsimd.c. - -Signed-off-by: Mark Brown -Reviewed-by: Catalin Marinas -Reviewed-by: Marc Zyngier -Link: https://lore.kernel.org/r/20221115094640.112848-2-broonie@kernel.org -Signed-off-by: Will Deacon -Stable-dep-of: 045aecdfcb2e ("arm64/ptrace: Don't enable SVE when setting streaming SVE") -Signed-off-by: Sasha Levin ---- - arch/arm64/include/asm/fpsimd.h | 1 + - arch/arm64/kernel/fpsimd.c | 23 +++++++++++++++++++++++ - arch/arm64/kvm/fpsimd.c | 3 ++- - 3 files changed, 26 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h -index 6f86b7ab6c28f..c07e4abaca3d6 100644 ---- a/arch/arm64/include/asm/fpsimd.h -+++ b/arch/arm64/include/asm/fpsimd.h -@@ -56,6 +56,7 @@ extern void fpsimd_signal_preserve_current_state(void); - extern void fpsimd_preserve_current_state(void); - extern void fpsimd_restore_current_state(void); - extern void fpsimd_update_current_state(struct user_fpsimd_state const *state); -+extern void fpsimd_kvm_prepare(void); - - extern void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *state, - void *sve_state, unsigned int sve_vl, -diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c -index 356036babd093..63d796ad95411 100644 ---- a/arch/arm64/kernel/fpsimd.c -+++ b/arch/arm64/kernel/fpsimd.c -@@ -1645,6 +1645,29 @@ void fpsimd_signal_preserve_current_state(void) - sve_to_fpsimd(current); - } - -+/* -+ * Called by KVM when entering the guest. -+ */ -+void fpsimd_kvm_prepare(void) -+{ -+ if (!system_supports_sve()) -+ return; -+ -+ /* -+ * KVM does not save host SVE state since we can only enter -+ * the guest from a syscall so the ABI means that only the -+ * non-saved SVE state needs to be saved. If we have left -+ * SVE enabled for performance reasons then update the task -+ * state to be FPSIMD only. -+ */ -+ get_cpu_fpsimd_context(); -+ -+ if (test_and_clear_thread_flag(TIF_SVE)) -+ sve_to_fpsimd(current); -+ -+ put_cpu_fpsimd_context(); -+} -+ - /* - * Associate current's FPSIMD context with this cpu - * The caller must have ownership of the cpu FPSIMD context before calling -diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c -index ec8e4494873d4..51ca78b31b952 100644 ---- a/arch/arm64/kvm/fpsimd.c -+++ b/arch/arm64/kvm/fpsimd.c -@@ -75,11 +75,12 @@ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu) - void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) - { - BUG_ON(!current->mm); -- BUG_ON(test_thread_flag(TIF_SVE)); - - if (!system_supports_fpsimd()) - return; - -+ fpsimd_kvm_prepare(); -+ - vcpu->arch.fp_state = FP_STATE_HOST_OWNED; - - vcpu_clear_flag(vcpu, HOST_SVE_ENABLED); --- -2.40.1 - diff --git a/queue-6.1/series b/queue-6.1/series index 1847fc472c6..3e208dd0fea 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -114,10 +114,10 @@ mtd-rawnand-rockchip-align-hwecc-vs.-raw-page-helper.patch mtd-rawnand-fsl_upm-fix-an-off-by-one-test-in-fun_ex.patch powerpc-mm-altmap-fix-altmap-boundary-check.patch drm-imx-ipuv3-fix-front-porch-adjustment-upon-hactiv.patch +drm-amd-display-ensure-that-planes-are-in-the-same-order.patch +drm-amd-display-skip-clear_payload_id_table-if-device-mst_en-is-0.patch selftests-rseq-play-nice-with-binaries-statically-li.patch f2fs-fix-to-set-flush_merge-opt-and-show-noflush_mer.patch f2fs-don-t-reset-unchangable-mount-option-in-f2fs_re.patch exfat-check-if-filename-entries-exceeds-max-filename.patch -kvm-arm64-discard-any-sve-state-when-entering-kvm-gu.patch -arm64-fpsimd-track-the-saved-fpsimd-state-type-separ.patch -arm64-ptrace-don-t-enable-sve-when-setting-streaming.patch +arm64-ptrace-don-t-enable-sve-when-setting-streaming-sve.patch