From: Mark Hatle Date: Wed, 2 Jul 2025 21:44:19 +0000 (-0500) Subject: u-boot: Dynamic RISC-V ISA configuration X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=de890297b392fcf7f5bd2d25d3c173373b93dd36;p=thirdparty%2Fopenembedded%2Fopenembedded-core-contrib.git u-boot: Dynamic RISC-V ISA configuration Allow the risc-v TUNE_FEATURES to select specific ISA (kconfig) selections via config fragments. This allows the following items to be selected dynamically: CONFIG_RISCV_ISA_C CONFIG_RISCV_ISA_F CONFIG_RISCV_ISA_D CONFIG_RISCV_ISA_ZBB CONFIG_RISCV_ISA_A CONFIG_RISCV_ISA_ZICBOM Signed-off-by: Mark Hatle Signed-off-by: Antonin Godard Signed-off-by: Richard Purdie --- diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg new file mode 100644 index 00000000000..fc45b64480e --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_A=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg new file mode 100644 index 00000000000..1cb459f6368 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_C=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg new file mode 100644 index 00000000000..ce90da23cef --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg @@ -0,0 +1,6 @@ +# CONFIG_RISCV_ISA_C is not set +# CONFIG_RISCV_ISA_F is not set +# CONFIG_RISCV_ISA_D is not set +# CONFIG_RISCV_ISA_ZBB is not set +# CONFIG_RISCV_ISA_A is not set +# CONFIG_RISCV_ISA_ZICBOM is not set diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg new file mode 100644 index 00000000000..fd25fa4e891 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_D=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg new file mode 100644 index 00000000000..dfa9876f821 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_F=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg new file mode 100644 index 00000000000..2b71b016f81 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_ZBB=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg new file mode 100644 index 00000000000..96daf04b202 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_ZICBOM=y diff --git a/meta/recipes-bsp/u-boot/u-boot-common.inc b/meta/recipes-bsp/u-boot/u-boot-common.inc index 617f5a60bb8..8600d4bab6e 100644 --- a/meta/recipes-bsp/u-boot/u-boot-common.inc +++ b/meta/recipes-bsp/u-boot/u-boot-common.inc @@ -16,6 +16,18 @@ SRCREV = "34820924edbc4ec7803eb89d9852f4b870fa760a" SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master;tag=v${PV}" +SRC_URI_RISCV = "\ + file://u-boot-riscv-isa_clear.cfg \ + ${@bb.utils.contains ("TUNE_FEATURES", "a", "file://u-boot-riscv-isa_a.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "f", "file://u-boot-riscv-isa_f.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "d", "file://u-boot-riscv-isa_d.cfg", "", d)} \ + ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://u-boot-riscv-isa_zbb.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \ + " + +SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" +SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" + B = "${WORKDIR}/build" inherit pkgconfig