From: Julian Seward <jseward@acm.org>
Date: Thu, 7 Apr 2005 02:03:52 +0000 (+0000)
Subject: Handle bsr{w,l,q} and allow bsfq.
X-Git-Tag: svn/VALGRIND_3_0_1^2~205
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=e043aabdfd408ec66d5b36faed20b7cc0af8fec5;p=thirdparty%2Fvalgrind.git

Handle bsr{w,l,q} and allow bsfq.


git-svn-id: svn://svn.valgrind.org/vex/trunk@1129
---

diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c
index e26efec052..f7f4b6f3f9 100644
--- a/VEX/priv/guest-amd64/toIR.c
+++ b/VEX/priv/guest-amd64/toIR.c
@@ -3330,6 +3330,7 @@ ULong dis_Grp8_Imm ( Prefix pfx,
    switch (sz) {
       case 2:  src_val &= 15; break;
       case 4:  src_val &= 31; break;
+      case 8:  src_val &= 63; break;
       default: *decode_OK = False; return delta;
    }
 
@@ -12863,9 +12864,10 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
          if (haveF2orF3(pfx)) goto decode_failure;
          delta = dis_bs_E_G ( pfx, sz, delta, True );
          break;
-//..       case 0xBD: /* BSR Gv,Ev */
-//..          delta = dis_bs_E_G ( sorb, sz, delta, False );
-//..          break;
+      case 0xBD: /* BSR Gv,Ev */
+         if (haveF2orF3(pfx)) goto decode_failure;
+         delta = dis_bs_E_G ( pfx, sz, delta, False );
+         break;
 
       /* =-=-=-=-=-=-=-=-=- BSWAP -=-=-=-=-=-=-=-=-=-=-= */
 
diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index 7e8602fb21..3b9d1ed72b 100644
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -1300,21 +1300,21 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
             addInstr(env, AMD64Instr_Bsfr64(True,src,dst));
             return dst;
          }
-//..          case Iop_Clz32: {
-//..             /* Count leading zeroes.  Do 'bsrl' to establish the index
-//..                of the highest set bit, and subtract that value from
-//..                31. */
-//..             HReg tmp = newVRegI(env);
-//..             HReg dst = newVRegI(env);
-//..             HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//..             addInstr(env, X86Instr_Bsfr32(False,src,tmp));
-//..             addInstr(env, X86Instr_Alu32R(Xalu_MOV, 
-//..                                           X86RMI_Imm(31), dst));
-//..             addInstr(env, X86Instr_Alu32R(Xalu_SUB,
-//..                                           X86RMI_Reg(tmp), dst));
-//..             return dst;
-//..          }
-//.. 
+         case Iop_Clz64: {
+            /* Count leading zeroes.  Do 'bsrq' to establish the index
+               of the highest set bit, and subtract that value from
+               63. */
+            HReg tmp = newVRegI(env);
+            HReg dst = newVRegI(env);
+            HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
+            addInstr(env, AMD64Instr_Bsfr64(False,src,tmp));
+            addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, 
+                                            AMD64RMI_Imm(63), dst));
+            addInstr(env, AMD64Instr_Alu64R(Aalu_SUB,
+                                            AMD64RMI_Reg(tmp), dst));
+            return dst;
+         }
+
 //..          case Iop_128to32: {
 //..             HReg      dst  = newVRegI(env);
 //..             HReg      vec  = iselVecExpr(env, e->Iex.Unop.arg);