From: Kyrylo Tkachov Date: Wed, 23 Apr 2014 15:20:25 +0000 (+0000) Subject: [ARM] Cortex-A8 rtx cost table X-Git-Tag: releases/gcc-5.1.0~7975 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=e0d8c86cd8a716fa1c936928f1157b53d134446b;p=thirdparty%2Fgcc.git [ARM] Cortex-A8 rtx cost table * config/arm/arm.c (cortexa8_extra_costs): New table. (arm_cortex_a8_tune): New tuning struct. * config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct. From-SVN: r209702 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5f86e3ec1557..f36108d748fa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-04-23 Kyrylo Tkachov + + * config/arm/arm.c (cortexa8_extra_costs): New table. + (arm_cortex_a8_tune): New tuning struct. + * config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct. + 2014-04-23 Kyrylo Tkachov * config/arm/arm.c (arm_new_rtx_costs): Handle FMA. diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 42f00b46326d..5bbc76ac269f 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -136,7 +136,7 @@ ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, 6M, FL_LDSCHED, v6m) ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, FL_LDSCHED, cortex_a5) ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7) -ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, FL_LDSCHED, cortex) +ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, FL_LDSCHED, cortex_a8) ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, FL_LDSCHED, cortex_a9) ARM_CORE("cortex-a12", cortexa12, cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12) ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 42df6fe0aa21..12c8730cbbfc 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1069,6 +1069,107 @@ const struct cpu_cost_table cortexa9_extra_costs = } }; +const struct cpu_cost_table cortexa8_extra_costs = +{ + /* ALU */ + { + 0, /* arith. */ + 0, /* logical. */ + COSTS_N_INSNS (1), /* shift. */ + 0, /* shift_reg. */ + COSTS_N_INSNS (1), /* arith_shift. */ + 0, /* arith_shift_reg. */ + COSTS_N_INSNS (1), /* log_shift. */ + 0, /* log_shift_reg. */ + 0, /* extend. */ + 0, /* extend_arith. */ + 0, /* bfi. */ + 0, /* bfx. */ + 0, /* clz. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (1), /* simple. */ + COSTS_N_INSNS (1), /* flag_setting. */ + COSTS_N_INSNS (1), /* extend. */ + COSTS_N_INSNS (1), /* add. */ + COSTS_N_INSNS (1), /* extend_add. */ + COSTS_N_INSNS (30) /* idiv. No HW div on Cortex A8. */ + }, + /* MULT DImode */ + { + 0, /* simple (N/A). */ + 0, /* flag_setting (N/A). */ + COSTS_N_INSNS (2), /* extend. */ + 0, /* add (N/A). */ + COSTS_N_INSNS (2), /* extend_add. */ + 0 /* idiv (N/A). */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (1), /* load. */ + COSTS_N_INSNS (1), /* load_sign_extend. */ + COSTS_N_INSNS (1), /* ldrd. */ + COSTS_N_INSNS (1), /* ldm_1st. */ + 1, /* ldm_regs_per_insn_1st. */ + 2, /* ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (1), /* loadf. */ + COSTS_N_INSNS (1), /* loadd. */ + COSTS_N_INSNS (1), /* load_unaligned. */ + COSTS_N_INSNS (1), /* store. */ + COSTS_N_INSNS (1), /* strd. */ + COSTS_N_INSNS (1), /* stm_1st. */ + 1, /* stm_regs_per_insn_1st. */ + 2, /* stm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (1), /* storef. */ + COSTS_N_INSNS (1), /* stored. */ + COSTS_N_INSNS (1) /* store_unaligned. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (36), /* div. */ + COSTS_N_INSNS (11), /* mult. */ + COSTS_N_INSNS (20), /* mult_addsub. */ + COSTS_N_INSNS (30), /* fma. */ + COSTS_N_INSNS (9), /* addsub. */ + COSTS_N_INSNS (3), /* fpconst. */ + COSTS_N_INSNS (3), /* neg. */ + COSTS_N_INSNS (6), /* compare. */ + COSTS_N_INSNS (4), /* widen. */ + COSTS_N_INSNS (4), /* narrow. */ + COSTS_N_INSNS (8), /* toint. */ + COSTS_N_INSNS (8), /* fromint. */ + COSTS_N_INSNS (8) /* roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (64), /* div. */ + COSTS_N_INSNS (16), /* mult. */ + COSTS_N_INSNS (25), /* mult_addsub. */ + COSTS_N_INSNS (30), /* fma. */ + COSTS_N_INSNS (9), /* addsub. */ + COSTS_N_INSNS (3), /* fpconst. */ + COSTS_N_INSNS (3), /* neg. */ + COSTS_N_INSNS (6), /* compare. */ + COSTS_N_INSNS (6), /* widen. */ + COSTS_N_INSNS (6), /* narrow. */ + COSTS_N_INSNS (8), /* toint. */ + COSTS_N_INSNS (8), /* fromint. */ + COSTS_N_INSNS (8) /* roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* alu. */ + } +}; + + const struct cpu_cost_table cortexa7_extra_costs = { @@ -1594,6 +1695,22 @@ const struct tune_params arm_cortex_tune = false, false /* Prefer 32-bit encodings. */ }; +const struct tune_params arm_cortex_a8_tune = +{ + arm_9e_rtx_costs, + &cortexa8_extra_costs, + NULL, /* Sched adj cost. */ + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ + &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ +}; + const struct tune_params arm_cortex_a7_tune = { arm_9e_rtx_costs,