From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Sun, 10 Sep 2023 14:07:10 +0000 (+0800)
Subject: RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm
X-Git-Tag: basepoints/gcc-15~6311
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=e390872aebcfebb7c9bc95d8fb7e44f2bec996d3;p=thirdparty%2Fgcc.git

RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid unnecessary slideup.
---

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 1ca3f1dc8df5..8a548f5d1a27 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2647,7 +2647,8 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d)
 
 	    For index = { 0, 2, 5, 6}, we need to slide op1 up before
 	    we apply compress approach.  */
-  bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1);
+  bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1)
+			&& !const_vec_duplicate_p (d->op1);
 
   /* If we leave it directly be handled by general gather,
      the code sequence will be: