From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date: Mon, 30 Jan 2017 06:36:02 +0000 (+0530)
Subject: ARM64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=e64259c957d82c6d0130967bc0315b100582a84c;p=thirdparty%2Fu-boot.git

ARM64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts
index abca7f2f4f9..7e7a9603caa 100644
--- a/arch/arm/dts/zynqmp-zcu102.dts
+++ b/arch/arm/dts/zynqmp-zcu102.dts
@@ -181,7 +181,7 @@
 		gtr_sel0 {
 			gpio-hog;
 			gpios = <0 0>;
-			output-high; /* PCIE = 0, DP = 1 */
+			output-low; /* PCIE = 0, DP = 1 */
 			line-name = "sel0";
 		};
 		gtr_sel1 {
@@ -837,7 +837,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 };
 
 &pcie {
-/*	status = "okay"; */
+	status = "okay";
 };
 
 &qspi {