From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Date: Tue, 16 Feb 2021 09:47:48 +0000 (+0530)
Subject: arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
X-Git-Tag: v5.12.4~484
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=e688a3953bd1219c46ceffc7a2f289b6461eb305;p=thirdparty%2Fkernel%2Fstable.git

arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity

[ Upstream commit 794d3e309e44c99158d0166b1717f297341cf3ab ]

As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/ca57409198477f7815e32a6a7467dcdc9b93dc4f.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 5ef460458f5c3..e8bf3f95c674c 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -153,7 +153,7 @@
 
 	pmu {
 		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	psci {