From: Alexandre Oliva Date: Wed, 25 Mar 2026 09:45:09 +0000 (-0300) Subject: [testsuite] [ppc] expect vectorization in gen-vect-11c.c with lp64 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=e6a0e0a8a41b3fa553c448c355eeddf88e27ca73;p=thirdparty%2Fgcc.git [testsuite] [ppc] expect vectorization in gen-vect-11c.c with lp64 The first loop in main gets stores "vectorized" on powerpc64 into full-word stores, even without any vector instruction support, so the test's expectation of no loop vectorization is not met. for gcc/testsuite/ChangeLog * gcc.dg/tree-ssa/gen-vect-11c.c: xfail the test for no vectorization on powerpc*-*-* && lp64. --- diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c index 22ff44cf66d..c0367ed2921 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c @@ -38,5 +38,6 @@ int main () return 0; } - -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail amdgcn*-*-* } } } */ +/* On power64, we vectorize pairs of ints into single non-vector registers. + That's not necessarily profitable, the costmodel may need adjustments. */ +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { amdgcn*-*-* || { powerpc*-*-* && lp64 } } } } } */