From: Taimur Hassan Date: Fri, 22 May 2026 09:57:40 +0000 (-0400) Subject: ddrm/amd/display: [FW Promotion] Release 0.1.61.0 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=e81a4c508e690bdb88410dfe51fe71a365f900c1;p=thirdparty%2Flinux.git ddrm/amd/display: [FW Promotion] Release 0.1.61.0 [Why & How] Update DMUB related command structure. Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 2f68438000ea2..6f0c4b602f898 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1,3 +1,12 @@ +/* + * Note: This header is the authoritative source for the DMUB firmware + * command interface. In the Linux kernel, it is maintained as an + * auto-generated copy from an AMD internal repository. + * + * This file follows Doxygen formatting for firmware standards and + * is NOT intended to be kernel-doc compliant. + */ + /* * Copyright 2019 Advanced Micro Devices, Inc. * @@ -94,6 +103,35 @@ */ #define ABM_MAX_NUM_OF_HG_BINS 64 +/** + * Flag from driver to indicate that CACP should be disabled gradually + * by slowly reversing all programming and pixel compensation. + */ +#define SET_CACP_PIPE_GRADUALLY_DISABLE 0 + +/** + * Flag from driver to indicate that CACP should be disabled immediately + * and undo all programming and pixel compensation. + */ +#define SET_CACP_PIPE_IMMEDIATELY_DISABLE 255 + +/** + * Flag from driver to indicate that CACP should be disabled immediately + * and keep the current programming and pixel compensation. + */ +#define SET_CACP_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 + +/** + * Flag from driver to indicate that CACP should be disabled immediately + * on the next abm vertical interrupt + */ +#define SET_CACP_PIPE_IMMEDIATE_ON_NEXT_DISABLE 253 + +/** + * Flag from driver to set the current CACP pipe index or CACP operating level. + */ +#define SET_CACP_PIPE_NORMAL 1 + /* Maximum number of SubVP streams */ #define DMUB_MAX_SUBVP_STREAMS 2 @@ -177,6 +215,26 @@ */ #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 +/** + * CACP control version legacy + */ +#define DMUB_CMD_CACP_CONTROL_VERSION_UNKNOWN 0x0 + +/** + * CACP control version with multi edp support + */ +#define DMUB_CMD_CACP_CONTROL_VERSION_1 0x1 + +/** + * CACP control mode with dynamic switch between v1 and v2 + */ +#define DMUB_CMD_CACP_CONTROL_MODE_0 0x0 + +/** + * CACP control version with forced configure to v1 on new ABM HW + */ +#define DMUB_CMD_CACP_CONTROL_MODE_1 0x1 + /** * Physical framebuffer address location, 64-bit. */ @@ -329,7 +387,7 @@ union dmub_addr { /* Flattened structure containing SOC BB parameters stored in the VBIOS * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. - * This also prevents alignment issues when new parameters are added to the SoC BB. + * This also prevents alighment issues when new parameters are added to the SoC BB. * The following parameters should be added since these values can't be obtained elsewhere: * -dml2_soc_power_management_parameters * -dml2_soc_vmin_clock_limits @@ -958,7 +1016,7 @@ union dmub_fw_meta { //============================================================================== #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) /** - * typedef dmub_trace_code_t - firmware trace code, 32-bits + * dmub_trace_code_t - firmware trace code, 32-bits */ typedef uint32_t dmub_trace_code_t; @@ -1170,7 +1228,7 @@ enum dmub_shared_state_feature_id { }; /** - * struct dmub_shared_state_ips_fw_signals - Firmware signals for IPS. + * struct dmub_shared_state_ips_fw - Firmware signals for IPS. */ union dmub_shared_state_ips_fw_signals { struct { @@ -1185,7 +1243,7 @@ union dmub_shared_state_ips_fw_signals { }; /** - * struct dmub_shared_state_ips_driver_signals - Firmware signals for IPS. + * struct dmub_shared_state_ips_signals - Firmware signals for IPS. */ union dmub_shared_state_ips_driver_signals { struct { @@ -1247,7 +1305,7 @@ struct dmub_shared_state_ips_driver { }; /* 248-bytes, fixed */ /** - * struct dmub_shared_state_cursor_offload_stream_v1 - Header metadata for cursor offload. + * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. */ struct dmub_shared_state_cursor_offload_stream_v1 { uint32_t last_write_idx; /**< Last write index */ @@ -1263,14 +1321,14 @@ struct dmub_shared_state_cursor_offload_v1 { }; /* 248-bytes, fixed */ /** - * struct dmub_shared_state_feature_common - Generic payload. + * enum dmub_shared_state_feature_common - Generic payload. */ struct dmub_shared_state_feature_common { uint32_t padding[62]; }; /* 248-bytes, fixed */ /** - * struct dmub_shared_state_feature_header - Feature description. + * enum dmub_shared_state_feature_header - Feature description. */ struct dmub_shared_state_feature_header { uint16_t id; /**< Feature ID */ @@ -1444,6 +1502,11 @@ enum dmub_gpint_command { */ DMUB_GPINT__REPLAY_RESIDENCY = 14, + /** + * DESC: Set CACP internal core configuration + */ + DMUB_GPINT__TRIGGER_CACP = 18, + /** * DESC: Copy bounding box to the host. * ARGS: Version of bounding box to copy @@ -1858,6 +1921,11 @@ enum dmub_cmd_type { */ DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, + /** + * Command type used for all CACP commands. + */ + DMUB_CMD__CACP = 87, + /** * Command type used for all PSP commands. */ @@ -1996,7 +2064,7 @@ struct dmub_cmd_read_modify_write_sequence { #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 /** - * struct dmub_rb_cmd_read_modify_write - Read modify write command. + * struct dmub_cmd_read_modify_write_sequence - Read modify write command. */ struct dmub_rb_cmd_read_modify_write { struct dmub_cmd_header header; /**< command header */ @@ -2007,7 +2075,7 @@ struct dmub_rb_cmd_read_modify_write { }; /* - * Update a register with specified masks and values sequence + * Update a register with specified masks and values sequeunce * * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword * @@ -2382,8 +2450,13 @@ struct dmub_cmd_lsdma_data { uint32_t tmz : 4; uint32_t cache_policy_src : 3; uint32_t cache_policy_dst : 3; - uint32_t pad1 : 22; - // DCC fields not included because linear mode on display does not support DCC + uint32_t data_format : 6; + uint32_t num_type : 3; + uint32_t read_compress : 2; + uint32_t write_compress : 2; + uint32_t max_com : 2; + uint32_t max_uncom : 1; + uint32_t pad1 : 6; } linear_copy_data; struct lsdma_linear_sub_window_copy_data { uint32_t src_lo; @@ -2411,9 +2484,13 @@ struct dmub_cmd_lsdma_data { uint32_t element_size : 3; uint32_t src_cache_policy : 3; uint32_t dst_cache_policy : 3; - uint32_t reserved0 : 19; - // Linear mode on display does not support compression so DCC related fields are not included. - // The DCC fields in the command packet will be zero'd at the time of constructing the packet. + uint32_t data_format : 6; + uint32_t num_type : 3; + uint32_t read_compress : 2; + uint32_t write_compress : 2; + uint32_t max_com : 2; + uint32_t max_uncom : 1; + uint32_t reserved0 : 3; } linear_sub_window_copy_data; struct lsdma_reg_write_data { uint32_t reg_addr; @@ -2877,7 +2954,7 @@ struct dmub_cmd_set_pixel_clock_data { }; /** - * struct dmub_rb_cmd_set_pixel_clock - Set pixel clock command. + * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. */ struct dmub_rb_cmd_set_pixel_clock { struct dmub_cmd_header header; /**< header */ @@ -3393,7 +3470,7 @@ struct dpia_bw_allocation_notify_data { }; /** - * union dpia_notification_data - DPIA Notification in Outbox command + * union dpia_notify_data_type - DPIA Notification in Outbox command */ union dpia_notification_data { /** @@ -3449,7 +3526,7 @@ struct dmub_rb_cmd_query_hpd_state { }; /** - * struct dmub_rb_cmd_hpd_sense_notify_data - HPD sense notification data. + * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. */ struct dmub_rb_cmd_hpd_sense_notify_data { uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ @@ -3493,7 +3570,7 @@ enum dmub_cmd_psr_type { /** * Set PSR level. - * PSR level is a 16-bit value dictated by driver that + * PSR level is a 16-bit value dicated by driver that * will enable/disable different functionality. */ DMUB_CMD__PSR_SET_LEVEL = 4, @@ -3538,6 +3615,7 @@ enum dmub_cmd_fams_type { DMUB_CMD__FAMS2_DRR_UPDATE = 5, DMUB_CMD__FAMS2_FLIP = 6, DMUB_CMD__FAMS2_IB_CONFIG = 7, + DMUB_CMD__FAMS2_IB_DEBUG_META = 8, }; /** @@ -3650,7 +3728,7 @@ struct dmub_cmd_psr_copy_settings_data { */ union dmub_psr_debug_flags debug; /** - * 16-bit value dictated by driver that will enable/disable different functionality. + * 16-bit value dicated by driver that will enable/disable different functionality. */ uint16_t psr_level; /** @@ -3690,7 +3768,7 @@ struct dmub_cmd_psr_copy_settings_data { */ uint8_t aux_inst; /** - * Determines if SMU optimizations are enabled/disabled. + * Determines if SMU optimzations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -3807,7 +3885,7 @@ struct dmub_rb_cmd_psr_copy_settings { */ struct dmub_cmd_psr_set_level_data { /** - * 16-bit value dictated by driver that will enable/disable different functionality. + * 16-bit value dicated by driver that will enable/disable different functionality. */ uint16_t psr_level; /** @@ -4185,7 +4263,7 @@ struct dmub_rb_cmd_update_cursor_info { */ struct dmub_cmd_psr_set_vtotal_data { /** - * 16-bit value dictated by driver that indicates the vtotal in PSR active requirement when screen idle.. + * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. */ uint16_t psr_vtotal_idle; /** @@ -4199,7 +4277,7 @@ struct dmub_cmd_psr_set_vtotal_data { */ uint8_t panel_inst; /* - * 16-bit value dictated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. + * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. */ uint16_t psr_vtotal_su; /** @@ -4423,6 +4501,7 @@ enum dmub_cmd_panel_replay_state_update_subtype { PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, PR_STATE_UPDATE_SYNC_MODE = 0x2, PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3, + PR_STATE_UPDATE_PSEUDO_VTOTAL = 0x4, }; enum dmub_cmd_panel_replay_general_subtype { @@ -4499,7 +4578,7 @@ struct dmub_cmd_replay_copy_settings_data { uint8_t aux_inst; /** * Panel Instance. - * Panel instance to identify which psr_state to use + * Panel isntance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4522,7 +4601,7 @@ struct dmub_cmd_replay_copy_settings_data { */ uint8_t dpphy_inst; /** - * Determines if SMU optimizations are enabled/disabled. + * Determines if SMU optimzations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -4612,7 +4691,7 @@ struct dmub_rb_cmd_smart_power_oled_enable_data { uint8_t enable; /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4651,7 +4730,7 @@ struct dmub_rb_cmd_replay_enable_data { uint8_t enable; /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4699,7 +4778,7 @@ struct dmub_rb_cmd_replay_enable { struct dmub_cmd_replay_set_power_opt_data { /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4719,7 +4798,7 @@ struct dmub_cmd_replay_set_power_opt_data { struct dmub_cmd_replay_set_timing_sync_data { /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4739,7 +4818,7 @@ struct dmub_cmd_replay_set_timing_sync_data { struct dmub_cmd_replay_set_pseudo_vtotal { /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4755,7 +4834,7 @@ struct dmub_cmd_replay_set_pseudo_vtotal { struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4769,7 +4848,7 @@ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { struct dmub_cmd_replay_set_general_cmd_data { /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4806,7 +4885,7 @@ struct dmub_rb_cmd_replay_set_power_opt { */ struct dmub_cmd_replay_set_coasting_vtotal_data { /** - * 16-bit value dictated by driver that indicates the coasting vtotal. + * 16-bit value dicated by driver that indicates the coasting vtotal. */ uint16_t coasting_vtotal; /** @@ -4815,12 +4894,12 @@ struct dmub_cmd_replay_set_coasting_vtotal_data { uint8_t cmd_version; /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; /** - * 16-bit value dictated by driver that indicates the coasting vtotal high byte part. + * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. */ uint16_t coasting_vtotal_high; /** @@ -4923,7 +5002,7 @@ struct dmub_rb_cmd_replay_set_general_cmd { struct dmub_cmd_replay_frameupdate_timer_data { /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4956,7 +5035,7 @@ struct dmub_rb_cmd_replay_set_frameupdate_timer { union dmub_replay_cmd_set { /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -5132,7 +5211,7 @@ struct dmub_hw_lock_inst_flags { uint8_t opp_inst; /** * OTG HW instance for global update lock. - * TODO: Remove, and reuse otg_inst. + * TODO: Remove, and re-use otg_inst. */ uint8_t dig_inst; /** @@ -6063,6 +6142,399 @@ struct dmub_rb_cmd_abm_set_event { struct dmub_cmd_abm_set_event_data abm_set_event_data; }; +/** + * CACP command sub-types. + */ +enum dmub_cmd_cacp_type { + /** + * Initialize parameters for CACP algorithm. + * Data is passed through an indirect buffer. + */ + DMUB_CMD__CACP_INIT_CONFIG = 0, + /** + * Set OTG and panel HW instance. + */ + DMUB_CMD__CACP_SET_PIPE = 1, + /** + * Set CACP operating/aggression level. + */ + DMUB_CMD__CACP_SET_LEVEL = 2, + /** + * Set event: full-screen/video mode/Hdr mode + */ + DMUB_CMD__CACP_SET_EVENT = 3, + + /** + * unregister vertical interrupt after steady state is reached + */ + DMUB_CMD__CACP_PAUSE = 4, + /** + * Set backlight: only for miniLED + */ + DMUB_CMD__CACP_SET_BACKLIGHT = 5, + /** + * Enable/disable fractional duty cycle for backlight PWM. + */ + DMUB_CMD__CACP_SET_PWM_FRAC = 6, + /** + * Get CACP Histogram + */ + DMUB_CMD__CACP_GET_HISTOGRAM = 7, +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PIPE command. + */ +struct dmub_cmd_cacp_set_pipe_data { + /** + * OTG HW instance. + */ + uint8_t otg_inst; + + /** + * Panel Control HW instance. + */ + uint8_t panel_inst; + + /** + * Controls how CACP will interpret a set pipe or set level command. + */ + uint8_t set_pipe_option; + + /** + * PwrSeq HW Instance. + */ + uint8_t pwrseq_inst; +}; + +/** + * Definition of a DMUB_CMD__CACP_SET_PIPE command. + */ +struct dmub_rb_cmd_cacp_set_pipe { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__CACP_PIPE command. + */ + struct dmub_cmd_cacp_set_pipe_data cacp_set_pipe_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_LEVEL command. + */ +struct dmub_cmd_cacp_set_level_data { + /** + * Set current cacp operating/aggression level. + */ + uint32_t level; + + /** + * CACP control version. + */ + uint8_t version; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__CACP_SET_LEVEL command. + */ +struct dmub_rb_cmd_cacp_set_level { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_LEVEL command. + */ + struct dmub_cmd_cacp_set_level_data cacp_set_level_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_EVENT command. + */ +struct dmub_cmd_cacp_set_event_data { + /** + * Full screen mode + */ + uint8_t full_screen_mode; + + /** + * VariBright Scaling Enable + */ + uint8_t vb_scaling_enable; + + /** + * HDR mode + */ + uint8_t hdr_mode; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Transition time info + */ + uint32_t trans_info; +}; + +/** + * Definition of a DMUB_CMD__CACP_SET_EVENT command. + */ +struct dmub_rb_cmd_cacp_set_event { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_EVENT command. + */ + struct dmub_cmd_cacp_set_event_data cacp_set_event_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__CACP_INIT_CONFIG command. + */ +struct dmub_cmd_cacp_init_config_data { + /** + * Location of indirect buffer used to pass init data to CACP. + */ + union dmub_addr src; + + /** + * Indirect buffer length. + */ + uint16_t bytes; + + /** + * CACP control version. + */ + uint8_t mode; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * CACP visual_confirm debug + */ + uint32_t visual_confirm; + + /** + * CACP customized str_scl params + */ + uint8_t strscl_valid; + uint8_t pad[3]; + uint8_t strscl_sdr[4]; + uint8_t strscl_hdr[4]; +}; + +/** + * Definition of a DMUB_CMD__CACP_INIT_CONFIG command. + */ +struct dmub_rb_cmd_cacp_init_config { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__CACP_INIT_CONFIG command. + */ + struct dmub_cmd_cacp_init_config_data cacp_init_config_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__CACP_PAUSE command. + */ + +struct dmub_cmd_cacp_pause_data { + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * OTG hw instance + */ + uint8_t otg_inst; + + /** + * Enable or disable CACP pause + */ + uint8_t enable; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad; +}; + +/** + * Definition of a DMUB_CMD__CACP_PAUSE command. + */ +struct dmub_rb_cmd_cacp_pause { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__CACP_PAUSE command. + */ + struct dmub_cmd_cacp_pause_data cacp_pause_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_BACKLIGHT command. + */ +struct dmub_cmd_cacp_set_backlight_data { + /** + * Number of frames to ramp to backlight user level. + */ + uint32_t frame_ramp; + + /** + * Requested backlight level from user. + */ + uint32_t backlight_user_level; + + /** + * ABM control version. + */ + uint8_t version; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__CACP_SET_BACKLIGHT command. + */ +struct dmub_rb_cmd_cacp_set_backlight { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_BACKLIGHT command. + */ + struct dmub_cmd_cacp_set_backlight_data cacp_set_backlight_data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PWM_FRAC command. + */ +struct dmub_cmd_cacp_set_pwm_frac_data { + /** + * Enable/disable fractional duty cycle for backlight PWM. + * TODO: Convert to uint8_t. + */ + uint32_t fractional_pwm; + + /** + * CACP control version. + */ + uint8_t version; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__CACP_SET_PWM_FRAC command. + */ +struct dmub_rb_cmd_cacp_set_pwm_frac { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__CACP_SET_PWM_FRAC command. + */ + struct dmub_cmd_cacp_set_pwm_frac_data cacp_set_pwm_frac_data; +}; + +/** + * Definition of a DMUB_CMD__CACP_GET_HISTOGRAM command. + */ +struct dmub_rb_cmd_cacp_get_histogram { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Address where Histogram should be copied. + */ + union dmub_addr dest; + + /** + * Type of Histogram being queried. + */ + enum dmub_abm_histogram_type histogram_type; + + /** + * Indirect buffer length. + */ + uint16_t bytes; + + /** + * eDP panel instance. + */ + uint8_t panel_inst; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad; +}; + /** * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. */ @@ -6328,7 +6800,7 @@ struct dmub_cmd_cable_id_input { }; /** - * struct dmub_cmd_cable_id_output - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. + * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. */ struct dmub_cmd_cable_id_output { uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ @@ -6619,7 +7091,7 @@ struct dmub_cmd_pr_enable_data { uint8_t enable; /** * Panel Instance. - * Panel instance to identify which replay_state to use + * Panel isntance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6697,7 +7169,7 @@ struct dmub_cmd_pr_copy_settings_data { uint8_t aux_inst; /** * Panel Instance. - * Panel instance to identify which psr_state to use + * Panel isntance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6706,7 +7178,7 @@ struct dmub_cmd_pr_copy_settings_data { */ uint8_t dpphy_inst; /** - * Determines if SMU optimizations are enabled/disabled. + * Determines if SMU optimzations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -6714,7 +7186,7 @@ struct dmub_cmd_pr_copy_settings_data { */ uint32_t line_time_in_ns; /* - * Use FSFT after pixel clk + * Use FSFT afftet pixel clk */ uint32_t pix_clk_100hz; /* @@ -6787,7 +7259,7 @@ union dmub_pr_runtime_flags { struct dmub_cmd_pr_update_state_data { /** * Panel Instance. - * Panel instance to identify which psr_state to use + * Panel isntance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6802,6 +7274,7 @@ struct dmub_cmd_pr_update_state_data { */ uint32_t coasting_vtotal; uint32_t sync_mode; + uint32_t pseudo_vtotal; union dmub_pr_runtime_flags pr_runtime_flags; }; @@ -6809,7 +7282,7 @@ struct dmub_cmd_pr_update_state_data { struct dmub_cmd_pr_general_cmd_data { /** * Panel Instance. - * Panel instance to identify which psr_state to use + * Panel isntance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -7134,6 +7607,47 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. */ struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; + + /** + * Definition of a DMUB_CMD__CACP_SET_PIPE command. + */ + struct dmub_rb_cmd_cacp_set_pipe cacp_set_pipe; + + /** + * Definition of a DMUB_CMD__CACP_SET_LEVEL command. + */ + struct dmub_rb_cmd_cacp_set_level cacp_set_level; + + /** + * Definition of a DMUB_CMD__CACP_SET_EVENT command. + */ + struct dmub_rb_cmd_cacp_set_event cacp_set_event; + + /** + * Definition of a DMUB_CMD__CACP_INIT_CONFIG command. + */ + struct dmub_rb_cmd_cacp_init_config cacp_init_config; + + /** + * Definition of a DMUB_CMD__CACP_PAUSE command. + */ + struct dmub_rb_cmd_cacp_pause cacp_pause; + + /** + * Definition of a DMUB_CMD__CACP_SET_BACKLIGHT command. + */ + struct dmub_rb_cmd_cacp_set_backlight cacp_set_backlight; + + /** + * Definition of a DMUB_CMD__CACP_SET_PWM_FRAC command. + */ + struct dmub_rb_cmd_cacp_set_pwm_frac cacp_set_pwm_frac; + + /** + * Definition of a DMUB_CMD__CACP_GET_HISTOGRAM command. + */ + struct dmub_rb_cmd_cacp_get_histogram cacp_get_histogram; + /** * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. */ @@ -7189,6 +7703,8 @@ union dmub_rb_cmd { struct dmub_rb_cmd_ib ib_fams2_config; + struct dmub_rb_cmd_ib ib_fams2_debug_meta; + struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; struct dmub_rb_cmd_fams2_flip fams2_flip;