From: Greg Kroah-Hartman Date: Wed, 26 Oct 2022 10:51:02 +0000 (+0200) Subject: 6.0-stable patches X-Git-Tag: v6.0.5~2 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=eb9ff7a545c01fc38deb6617d4f470323e762072;p=thirdparty%2Fkernel%2Fstable-queue.git 6.0-stable patches added patches: clk-tegra-fix-tegra-pwm-parent-clock.patch --- diff --git a/queue-6.0/clk-tegra-fix-tegra-pwm-parent-clock.patch b/queue-6.0/clk-tegra-fix-tegra-pwm-parent-clock.patch new file mode 100644 index 00000000000..040f8177a24 --- /dev/null +++ b/queue-6.0/clk-tegra-fix-tegra-pwm-parent-clock.patch @@ -0,0 +1,96 @@ +From c461c677a8cb19026fd06741a23ff32d0759342b Mon Sep 17 00:00:00 2001 +From: Jon Hunter +Date: Mon, 10 Oct 2022 11:00:46 +0100 +Subject: clk: tegra: Fix Tegra PWM parent clock +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jon Hunter + +commit c461c677a8cb19026fd06741a23ff32d0759342b upstream. + +Commit 8c193f4714df ("pwm: tegra: Optimize period calculation") updated +the period calculation in the Tegra PWM driver and now returns an error +if the period requested is less than minimum period supported. This is +breaking PWM support on various Tegra platforms. For example, on the +Tegra210 Jetson Nano platform this is breaking the PWM fan support and +probing the PWM fan driver now fails ... + + pwm-fan pwm-fan: Failed to configure PWM: -22 + pwm-fan: probe of pwm-fan failed with error -22 + +The problem is that the default parent clock for the PWM on Tegra210 is +a 32kHz clock and is unable to support the requested PWM period. + +Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by +updating the parent clock for the PWM to be the PLL_P. + +Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation") +Signed-off-by: Jon Hunter +Tested-by: Robert Eckelmann # TF101 T20 +Tested-by: Antoni Aloy Torrens # TF101 T20 +Tested-by: Svyatoslav Ryhel # TF201 T30 +Tested-by: Andreas Westman Dorcsak # TF700T T3 +Link: https://lore.kernel.org/r/20221010100046.6477-1-jonathanh@nvidia.com +Acked-by: Uwe Kleine-König +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/tegra/clk-tegra114.c | 1 + + drivers/clk/tegra/clk-tegra124.c | 1 + + drivers/clk/tegra/clk-tegra20.c | 1 + + drivers/clk/tegra/clk-tegra210.c | 1 + + drivers/clk/tegra/clk-tegra30.c | 1 + + 5 files changed, 5 insertions(+) + +--- a/drivers/clk/tegra/clk-tegra114.c ++++ b/drivers/clk/tegra/clk-tegra114.c +@@ -1166,6 +1166,7 @@ static struct tegra_clk_init_table init_ + { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, + { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, + { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, ++ { TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 }, + /* must be the last entry */ + { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 }, + }; +--- a/drivers/clk/tegra/clk-tegra124.c ++++ b/drivers/clk/tegra/clk-tegra124.c +@@ -1330,6 +1330,7 @@ static struct tegra_clk_init_table commo + { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, + { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, + { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, ++ { TEGRA124_CLK_PWM, TEGRA124_CLK_PLL_P, 408000000, 0 }, + /* must be the last entry */ + { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, + }; +--- a/drivers/clk/tegra/clk-tegra20.c ++++ b/drivers/clk/tegra/clk-tegra20.c +@@ -1044,6 +1044,7 @@ static struct tegra_clk_init_table init_ + { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, + { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, + { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, ++ { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, + /* must be the last entry */ + { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, + }; +--- a/drivers/clk/tegra/clk-tegra210.c ++++ b/drivers/clk/tegra/clk-tegra210.c +@@ -3597,6 +3597,7 @@ static struct tegra_clk_init_table init_ + { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, + { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 }, + { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 }, ++ { TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 }, + /* This MUST be the last entry. */ + { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, + }; +--- a/drivers/clk/tegra/clk-tegra30.c ++++ b/drivers/clk/tegra/clk-tegra30.c +@@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_ + { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, + { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, + { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, ++ { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, + /* must be the last entry */ + { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, + }; diff --git a/queue-6.0/series b/queue-6.0/series index 7953aa9e38a..4178bad8c81 100644 --- a/queue-6.0/series +++ b/queue-6.0/series @@ -1 +1,2 @@ +clk-tegra-fix-tegra-pwm-parent-clock.patch revert-btrfs-call-__btrfs_remove_free_space_cache_locked-on.patch