From: Kito Cheng <kito.cheng@sifive.com>
Date: Thu, 27 Apr 2023 14:00:39 +0000 (+0800)
Subject: Docs: Add vector register constarint for asm operands
X-Git-Tag: releases/gcc-13.2.0~323
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=eed151c062b908cdd4a6a91d79514363b3e545f8;p=thirdparty%2Fgcc.git

Docs: Add vector register constarint for asm operands

`vr`, `vm` and `vd` constarint for vector register constarint, those 3
constarint has implemented on LLVM as well.

gcc/ChangeLog:

	* doc/md.texi (RISC-V): Add vr, vm, vd constarint.

(cherry picked from commit e8511cbba692a9f3ff4d9c74e902fab03f154bbd)
---

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 07bf8bdebffb..cc4a93a87638 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3535,6 +3535,15 @@ An address that is held in a general-purpose register.
 @item S
 A constraint that matches an absolute symbolic address.
 
+@item vr
+A vector register (if available)..
+
+@item vd
+A vector register, excluding v0 (if available).
+
+@item vm
+A vector register, only v0 (if available).
+
 @end table
 
 @item RX---@file{config/rx/constraints.md}