From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 7 May 2013 13:01:20 +0000 (+0200)
Subject: zynq: Do not enable icache
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=ef2d9cbb668fa1937a1d2317c53b6c2926d1b763;p=thirdparty%2Fu-boot.git

zynq: Do not enable icache

icache is already turned on.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index e8f4c19d490..156cb0099ab 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -55,3 +55,11 @@ void reset_cpu(ulong addr)
 	while (1)
 		;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+        /* Enable D-cache. I-cache is already enabled in start.S */
+        dcache_enable();
+}
+#endif
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 979ddb13928..da2abe4c066 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -84,8 +84,6 @@ int board_init(void)
 	writel(0x00, 0xe000a040);
 	writel(0x80, 0xe000a040);
 
-	icache_enable();
-
 #ifdef CONFIG_FPGA
 	fpga_init();
 	fpga_add(fpga_xilinx, &fpga);
diff --git a/include/configs/petalogix-arm-auto.h b/include/configs/petalogix-arm-auto.h
index 13b797aa584..c352701333e 100644
--- a/include/configs/petalogix-arm-auto.h
+++ b/include/configs/petalogix-arm-auto.h
@@ -23,8 +23,17 @@
 # endif
 #endif
 
+#define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE	32 /* Assuming bytes? */
 
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_L2CACHE_OFF
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE  0xf8f02000
+#endif
+
 #define CONFIG_NR_DRAM_BANKS		1
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/zynq_common.h b/include/configs/zynq_common.h
index 4e87cbe9620..fe638c6594c 100644
--- a/include/configs/zynq_common.h
+++ b/include/configs/zynq_common.h
@@ -250,10 +250,18 @@
 #define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
 #define CONFIG_SYS_LOAD_ADDR		0 /* default? */
 
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0xf8f02000
+#endif
+
 /* Physical Memory map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0