From: Jiufu Guo <guojiufu@linux.ibm.com>
Date: Tue, 14 Jan 2025 00:16:16 +0000 (-0600)
Subject: rs6000: Add clobber and guard for vsx_stxvd2x4_le_const [PR116030]
X-Git-Tag: basepoints/gcc-16~2670
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=f12bb6c26b86c616e4de8c542804cb5b5c9ebdc6;p=thirdparty%2Fgcc.git

rs6000: Add clobber and guard for vsx_stxvd2x4_le_const [PR116030]

Previously, vsx_stxvd2x4_le_const_<mode> was introduced for 'split1' pass,
so it is guarded by "can_create_pseudo_p ()".  While it would be possible
to match the pattern of this insn during/after RA, this insn could be
updated to make it work for split pass after RA.

And this insn would not be the best choice if the address has alignment like
"&(-16)", so "!altivec_indexed_or_indirect_operand" is added to guard this insn.

2025-01-13  Jiufu Guo  <guojiufu@linux.ibm.com>

gcc/
	PR target/116030
	* config/rs6000/vsx.md (vsx_stxvd2x4_le_const_<mode>): Add clobber
	and guard with !altivec_indexed_or_indirect_operand.

gcc/testsuite/
	PR target/116030
	* gcc.target/powerpc/pr116030.c: New test.
---

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d4e0190484a0..dd3573b80868 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3453,12 +3453,13 @@
 
 (define_insn_and_split "vsx_stxvd2x4_le_const_<mode>"
   [(set (match_operand:VSX_W 0 "memory_operand" "=Z")
-	(match_operand:VSX_W 1 "immediate_operand" "W"))]
+	(match_operand:VSX_W 1 "immediate_operand" "W"))
+   (clobber (match_scratch:VSX_W 2 "=wa"))]
   "!BYTES_BIG_ENDIAN
    && VECTOR_MEM_VSX_P (<MODE>mode)
    && !TARGET_P9_VECTOR
-   && const_vec_duplicate_p (operands[1])
-   && can_create_pseudo_p ()"
+   && !altivec_indexed_or_indirect_operand (operands[0], <MODE>mode)
+   && const_vec_duplicate_p (operands[1])"
   "#"
   "&& 1"
   [(set (match_dup 2)
@@ -3471,7 +3472,8 @@
 {
   /* Here all the constants must be loaded without memory.  */
   gcc_assert (easy_altivec_constant (operands[1], <MODE>mode));
-  operands[2] = gen_reg_rtx (<MODE>mode);
+  if (GET_CODE (operands[2]) == SCRATCH)
+    operands[2] = gen_reg_rtx (<MODE>mode);
 }
   [(set_attr "type" "vecstore")
    (set_attr "length" "8")])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr116030.c b/gcc/testsuite/gcc.target/powerpc/pr116030.c
new file mode 100644
index 000000000000..da27106a5a75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr116030.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power8 -Os -fno-forward-propagate -ftrivial-auto-var-init=zero" } */
+/* { dg-require-effective-target dfp } */
+
+/* Verify we do not ICE on the tests below.  */
+
+/* { dg-final { scan-assembler-not "rldicr" { target { le } } } } */
+/* { dg-final { scan-assembler-not "stxvd2x" { target { le } } } } */
+
+union U128
+{
+  _Decimal128 d;
+  unsigned long long int u[2];
+};
+
+union U128
+foo ()
+{
+  volatile union U128 u128;
+  u128.d = 0.9999999999999999999999999999999999e+39DL;
+  return u128;
+}