From: Sasha Levin Date: Sat, 19 Nov 2022 17:24:34 +0000 (-0500) Subject: Fixes for 5.10 X-Git-Tag: v4.19.266~51 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=f12f8bda342dfc875c54166556789bb97c73b8eb;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.10 Signed-off-by: Sasha Levin --- diff --git a/queue-5.10/alsa-hda-realtek-fix-speakers-and-micmute-on-hp-855-.patch b/queue-5.10/alsa-hda-realtek-fix-speakers-and-micmute-on-hp-855-.patch new file mode 100644 index 00000000000..8b0f8c7db3d --- /dev/null +++ b/queue-5.10/alsa-hda-realtek-fix-speakers-and-micmute-on-hp-855-.patch @@ -0,0 +1,71 @@ +From 07043c9f681860b4bfc57a91ddcd42a9d0b02bee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 14 Jan 2022 19:50:50 +0300 +Subject: ALSA: hda/realtek: fix speakers and micmute on HP 855 G8 + +From: Alexander Sergeyev + +[ Upstream commit 91502a9a0b0d5252cf3f32ebd898823c2f5aadab ] + +There are several PCI ids associated with HP EliteBook 855 G8 Notebook +PC. Commit 0e68c4b11f1e6 ("ALSA: hda/realtek: fix mute/micmute LEDs for +HP 855 G8") covers 0x103c:0x8896, while this commit covers 0x103c:0x8895 +which needs some additional work on top of the quirk from 0e68c4b11f1e6. + +Note that the device can boot up with working speakers and micmute LED +without this patch, but the success rate would be quite low (order of +16 working boots across 709 boots) at least for the built-in drivers +scenario. This also means that there are some timing issues during early +boot and this patch is a workaround. + +With this patch applied speakers and headphones are consistenly working, +as well as mute/micmute LEDs and the internal microphone. + +Signed-off-by: Alexander Sergeyev +Link: https://lore.kernel.org/r/20220114165050.ouw2nknuspclynro@localhost.localdomain +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_realtek.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index e3f6b930ad4a..d427e8939a0e 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -6883,6 +6883,7 @@ enum { + ALC256_FIXUP_MIC_NO_PRESENCE_AND_RESUME, + ALC285_FIXUP_LEGION_Y9000X_SPEAKERS, + ALC285_FIXUP_LEGION_Y9000X_AUTOMUTE, ++ ALC285_FIXUP_HP_SPEAKERS_MICMUTE_LED, + }; + + /* A special fixup for Lenovo C940 and Yoga Duet 7; +@@ -8693,6 +8694,16 @@ static const struct hda_fixup alc269_fixups[] = { + .chained = true, + .chain_id = ALC269_FIXUP_HEADSET_MODE_NO_HP_MIC + }, ++ [ALC285_FIXUP_HP_SPEAKERS_MICMUTE_LED] = { ++ .type = HDA_FIXUP_VERBS, ++ .v.verbs = (const struct hda_verb[]) { ++ { 0x20, AC_VERB_SET_COEF_INDEX, 0x19 }, ++ { 0x20, AC_VERB_SET_PROC_COEF, 0x8e11 }, ++ { } ++ }, ++ .chained = true, ++ .chain_id = ALC285_FIXUP_HP_MUTE_LED, ++ }, + }; + + static const struct snd_pci_quirk alc269_fixup_tbl[] = { +@@ -8915,6 +8926,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { + SND_PCI_QUIRK(0x103c, 0x8870, "HP ZBook Fury 15.6 Inch G8 Mobile Workstation PC", ALC285_FIXUP_HP_GPIO_AMP_INIT), + SND_PCI_QUIRK(0x103c, 0x8873, "HP ZBook Studio 15.6 Inch G8 Mobile Workstation PC", ALC285_FIXUP_HP_GPIO_AMP_INIT), + SND_PCI_QUIRK(0x103c, 0x888d, "HP ZBook Power 15.6 inch G8 Mobile Workstation PC", ALC236_FIXUP_HP_GPIO_LED), ++ SND_PCI_QUIRK(0x103c, 0x8895, "HP EliteBook 855 G8 Notebook PC", ALC285_FIXUP_HP_SPEAKERS_MICMUTE_LED), + SND_PCI_QUIRK(0x103c, 0x8896, "HP EliteBook 855 G8 Notebook PC", ALC285_FIXUP_HP_MUTE_LED), + SND_PCI_QUIRK(0x103c, 0x89aa, "HP EliteBook 630 G9", ALC236_FIXUP_HP_GPIO_LED), + SND_PCI_QUIRK(0x1043, 0x103e, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), +-- +2.35.1 + diff --git a/queue-5.10/drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch b/queue-5.10/drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch new file mode 100644 index 00000000000..bea0c724f41 --- /dev/null +++ b/queue-5.10/drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch @@ -0,0 +1,46 @@ +From c8ad8d3be64e8f660e78b7f07cf89e8135d6501e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 20:31:36 +0800 +Subject: drm/amd/pm: disable BACO entry/exit completely on several sienna + cichlid cards + +From: Guchun Chen + +[ Upstream commit 7bb91228291aa95bfee3b9d5710887673711c74c ] + +To avoid hardware intermittent failures. + +Signed-off-by: Guchun Chen +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Stable-dep-of: 0c85c067c9d9 ("drm/amdgpu: disable BACO on special BEIGE_GOBY card") +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index def32b6897f9..91026d0c1c79 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -309,6 +309,17 @@ static void sienna_cichlid_check_bxco_support(struct smu_context *smu) + smu_baco->platform_support = + (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : + false; ++ ++ /* ++ * Disable BACO entry/exit completely on below SKUs to ++ * avoid hardware intermittent failures. ++ */ ++ if (((adev->pdev->device == 0x73A1) && ++ (adev->pdev->revision == 0x00)) || ++ ((adev->pdev->device == 0x73BF) && ++ (adev->pdev->revision == 0xCF))) ++ smu_baco->platform_support = false; ++ + } + } + +-- +2.35.1 + diff --git a/queue-5.10/drm-amd-pm-read-bif-strap-also-for-baco-check.patch b/queue-5.10/drm-amd-pm-read-bif-strap-also-for-baco-check.patch new file mode 100644 index 00000000000..73e38dea2aa --- /dev/null +++ b/queue-5.10/drm-amd-pm-read-bif-strap-also-for-baco-check.patch @@ -0,0 +1,196 @@ +From 1c114a63985246e6a8604b8f0aa12dae8b33fc4f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 4 Jun 2021 15:33:48 +0800 +Subject: drm/amd/pm: Read BIF STRAP also for BACO check + +From: Lijo Lazar + +[ Upstream commit 458020dd4f7109693d4857ed320398e662e8899a ] + +Avoid reading BIF STRAP each time for BACO capability. Read the STRAP +value while checking BACO capability in PPTable. + +Signed-off-by: Lijo Lazar +Reviewed-by: Evan Quan +Signed-off-by: Alex Deucher +Stable-dep-of: 0c85c067c9d9 ("drm/amdgpu: disable BACO on special BEIGE_GOBY card") +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 25 ++++++++++++----- + .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 27 ++++++++++++++----- + .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 27 ++++++++++++++----- + 3 files changed, 59 insertions(+), 20 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +index 1c526cb239e0..3a31058b029e 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +@@ -379,16 +379,31 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) + return 0; + } + +-static int arcturus_check_powerplay_table(struct smu_context *smu) ++static void arcturus_check_bxco_support(struct smu_context *smu) + { + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_powerplay_table *powerplay_table = + table_context->power_play_table; + struct smu_baco_context *smu_baco = &smu->smu_baco; ++ struct amdgpu_device *adev = smu->adev; ++ uint32_t val; + + if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) +- smu_baco->platform_support = true; ++ powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { ++ val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); ++ smu_baco->platform_support = ++ (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : ++ false; ++ } ++} ++ ++static int arcturus_check_powerplay_table(struct smu_context *smu) ++{ ++ struct smu_table_context *table_context = &smu->smu_table; ++ struct smu_11_0_powerplay_table *powerplay_table = ++ table_context->power_play_table; ++ ++ arcturus_check_bxco_support(smu); + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; +@@ -2131,13 +2146,11 @@ static void arcturus_get_unique_id(struct smu_context *smu) + static bool arcturus_is_baco_supported(struct smu_context *smu) + { + struct amdgpu_device *adev = smu->adev; +- uint32_t val; + + if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev)) + return false; + +- val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); +- return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; ++ return true; + } + + static int arcturus_set_df_cstate(struct smu_context *smu, +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +index 2937784bc824..a7773b6453d5 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +@@ -338,19 +338,34 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, + return 0; + } + +-static int navi10_check_powerplay_table(struct smu_context *smu) ++static void navi10_check_bxco_support(struct smu_context *smu) + { + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_powerplay_table *powerplay_table = + table_context->power_play_table; + struct smu_baco_context *smu_baco = &smu->smu_baco; ++ struct amdgpu_device *adev = smu->adev; ++ uint32_t val; ++ ++ if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || ++ powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { ++ val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); ++ smu_baco->platform_support = ++ (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : ++ false; ++ } ++} ++ ++static int navi10_check_powerplay_table(struct smu_context *smu) ++{ ++ struct smu_table_context *table_context = &smu->smu_table; ++ struct smu_11_0_powerplay_table *powerplay_table = ++ table_context->power_play_table; + + if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) +- smu_baco->platform_support = true; ++ navi10_check_bxco_support(smu); + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; +@@ -1948,13 +1963,11 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, + static bool navi10_is_baco_supported(struct smu_context *smu) + { + struct amdgpu_device *adev = smu->adev; +- uint32_t val; + + if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) + return false; + +- val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); +- return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; ++ return true; + } + + static int navi10_set_default_od_settings(struct smu_context *smu) +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index 834ac633281c..def32b6897f9 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -294,19 +294,34 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, + return 0; + } + +-static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) ++static void sienna_cichlid_check_bxco_support(struct smu_context *smu) + { + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_7_powerplay_table *powerplay_table = + table_context->power_play_table; + struct smu_baco_context *smu_baco = &smu->smu_baco; ++ struct amdgpu_device *adev = smu->adev; ++ uint32_t val; ++ ++ if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || ++ powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) { ++ val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); ++ smu_baco->platform_support = ++ (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : ++ false; ++ } ++} ++ ++static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) ++{ ++ struct smu_table_context *table_context = &smu->smu_table; ++ struct smu_11_0_7_powerplay_table *powerplay_table = ++ table_context->power_play_table; + + if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) +- smu_baco->platform_support = true; ++ sienna_cichlid_check_bxco_support(smu); + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; +@@ -1739,13 +1754,11 @@ static int sienna_cichlid_run_btc(struct smu_context *smu) + static bool sienna_cichlid_is_baco_supported(struct smu_context *smu) + { + struct amdgpu_device *adev = smu->adev; +- uint32_t val; + + if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) + return false; + +- val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); +- return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; ++ return true; + } + + static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) +-- +2.35.1 + diff --git a/queue-5.10/drm-amd-pm-support-power-source-switch-on-sienna-cic.patch b/queue-5.10/drm-amd-pm-support-power-source-switch-on-sienna-cic.patch new file mode 100644 index 00000000000..c9f7a1eab29 --- /dev/null +++ b/queue-5.10/drm-amd-pm-support-power-source-switch-on-sienna-cic.patch @@ -0,0 +1,45 @@ +From 1660455744b5fad014ef6bcbaee5fb0ee76dabdd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 7 Dec 2020 16:21:03 +0800 +Subject: drm/amd/pm: support power source switch on Sienna Cichlid + +From: Evan Quan + +[ Upstream commit 18a4b3de5fc1c63c80e3be0673886431a56e4307 ] + +Enable power source switch on Sienna Cichlid. + +Signed-off-by: Evan Quan +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Stable-dep-of: 0c85c067c9d9 ("drm/amdgpu: disable BACO on special BEIGE_GOBY card") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index 49d7fa1d0842..834ac633281c 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -301,6 +301,9 @@ static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) + table_context->power_play_table; + struct smu_baco_context *smu_baco = &smu->smu_baco; + ++ if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) ++ smu->dc_controlled_by_gpio = true; ++ + if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || + powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) + smu_baco->platform_support = true; +@@ -2806,6 +2809,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { + .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, + .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, + .run_btc = sienna_cichlid_run_btc, ++ .set_power_source = smu_v11_0_set_power_source, + .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, + .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, + .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, +-- +2.35.1 + diff --git a/queue-5.10/drm-amdgpu-disable-baco-on-special-beige_goby-card.patch b/queue-5.10/drm-amdgpu-disable-baco-on-special-beige_goby-card.patch new file mode 100644 index 00000000000..bc99f5b2b11 --- /dev/null +++ b/queue-5.10/drm-amdgpu-disable-baco-on-special-beige_goby-card.patch @@ -0,0 +1,39 @@ +From 3365d79aef893c0f3980e50e95075125f8b46fc1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 7 Nov 2022 16:46:59 +0800 +Subject: drm/amdgpu: disable BACO on special BEIGE_GOBY card + +From: Guchun Chen + +[ Upstream commit 0c85c067c9d9d7a1b2cc2e01a236d5d0d4a872b5 ] + +Still avoid intermittent failure. + +Signed-off-by: Guchun Chen +Reviewed-by: Lijo Lazar +Acked-by: Evan Quan +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index 91026d0c1c79..45c815262200 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -317,7 +317,9 @@ static void sienna_cichlid_check_bxco_support(struct smu_context *smu) + if (((adev->pdev->device == 0x73A1) && + (adev->pdev->revision == 0x00)) || + ((adev->pdev->device == 0x73BF) && +- (adev->pdev->revision == 0xCF))) ++ (adev->pdev->revision == 0xCF)) || ++ ((adev->pdev->device == 0x7422) && ++ (adev->pdev->revision == 0x00))) + smu_baco->platform_support = false; + + } +-- +2.35.1 + diff --git a/queue-5.10/mmc-sdhci-esdhc-imx-use-the-correct-host-caps-for-mm.patch b/queue-5.10/mmc-sdhci-esdhc-imx-use-the-correct-host-caps-for-mm.patch new file mode 100644 index 00000000000..b90c68beb38 --- /dev/null +++ b/queue-5.10/mmc-sdhci-esdhc-imx-use-the-correct-host-caps-for-mm.patch @@ -0,0 +1,48 @@ +From 2c3a3de2ec71dd71d4ff37922177f6a06c89441f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Nov 2022 15:45:03 +0800 +Subject: mmc: sdhci-esdhc-imx: use the correct host caps for + MMC_CAP_8_BIT_DATA + +From: Haibo Chen + +[ Upstream commit f002f45a00ee14214d96b18b9a555fe2c56afb20 ] + +MMC_CAP_8_BIT_DATA belongs to struct mmc_host, not struct sdhci_host. +So correct it here. + +Fixes: 1ed5c3b22fc7 ("mmc: sdhci-esdhc-imx: Propagate ESDHC_FLAG_HS400* only on 8bit bus") +Signed-off-by: Haibo Chen +Cc: stable@vger.kernel.org +Acked-by: Adrian Hunter +Link: https://lore.kernel.org/r/1667893503-20583-1-git-send-email-haibo.chen@nxp.com +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/sdhci-esdhc-imx.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c +index 449562122adc..1f1bdd34dd55 100644 +--- a/drivers/mmc/host/sdhci-esdhc-imx.c ++++ b/drivers/mmc/host/sdhci-esdhc-imx.c +@@ -1621,14 +1621,14 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) + if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) + host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; + +- if (host->caps & MMC_CAP_8_BIT_DATA && ++ if (host->mmc->caps & MMC_CAP_8_BIT_DATA && + imx_data->socdata->flags & ESDHC_FLAG_HS400) + host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; + + if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) + host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; + +- if (host->caps & MMC_CAP_8_BIT_DATA && ++ if (host->mmc->caps & MMC_CAP_8_BIT_DATA && + imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { + host->mmc->caps2 |= MMC_CAP2_HS400_ES; + host->mmc_host_ops.hs400_enhanced_strobe = +-- +2.35.1 + diff --git a/queue-5.10/mtd-spi-nor-intel-spi-disable-write-protection-only-.patch b/queue-5.10/mtd-spi-nor-intel-spi-disable-write-protection-only-.patch new file mode 100644 index 00000000000..a75bad96fd9 --- /dev/null +++ b/queue-5.10/mtd-spi-nor-intel-spi-disable-write-protection-only-.patch @@ -0,0 +1,320 @@ +From 1fadd7b95bd333c710c9ae991f5acc5dc5303bfc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 9 Feb 2022 15:27:04 +0300 +Subject: mtd: spi-nor: intel-spi: Disable write protection only if asked + +From: Mika Westerberg + +[ Upstream commit cd149eff8d2201a63c074a6d9d03e52926aa535d ] + +Currently the driver tries to disable the BIOS write protection +automatically even if this is not what the user wants. For this reason +modify the driver so that by default it does not touch the write +protection. Only if specifically asked by the user (setting writeable=1 +command line parameter) the driver tries to disable the BIOS write +protection. + +Signed-off-by: Mika Westerberg +Reviewed-by: Andy Shevchenko +Reviewed-by: Mauro Lima +Reviewed-by: Tudor Ambarus +Acked-by: Lee Jones +Link: https://lore.kernel.org/r/20220209122706.42439-2-mika.westerberg@linux.intel.com +Signed-off-by: Mark Brown +Stable-dep-of: 92a66cbf6b30 ("spi: intel: Use correct mask for flash and protected regions") +Signed-off-by: Sasha Levin +--- + drivers/mfd/lpc_ich.c | 59 +++++++++++++++++-- + .../mtd/spi-nor/controllers/intel-spi-pci.c | 29 +++++---- + drivers/mtd/spi-nor/controllers/intel-spi.c | 41 ++++++------- + include/linux/platform_data/intel-spi.h | 6 +- + 4 files changed, 96 insertions(+), 39 deletions(-) + +diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c +index 3bbb29a7e7a5..2411b7a2e6f4 100644 +--- a/drivers/mfd/lpc_ich.c ++++ b/drivers/mfd/lpc_ich.c +@@ -63,6 +63,8 @@ + #define SPIBASE_BYT 0x54 + #define SPIBASE_BYT_SZ 512 + #define SPIBASE_BYT_EN BIT(1) ++#define BYT_BCR 0xfc ++#define BYT_BCR_WPD BIT(0) + + #define SPIBASE_LPT 0x3800 + #define SPIBASE_LPT_SZ 512 +@@ -1083,12 +1085,57 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) + return ret; + } + ++static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data) ++{ ++ u32 val; ++ ++ val = readl(base + BYT_BCR); ++ if (!(val & BYT_BCR_WPD)) { ++ val |= BYT_BCR_WPD; ++ writel(val, base + BYT_BCR); ++ val = readl(base + BYT_BCR); ++ } ++ ++ return val & BYT_BCR_WPD; ++} ++ ++static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data) ++{ ++ struct pci_dev *pdev = data; ++ u32 bcr; ++ ++ pci_read_config_dword(pdev, BCR, &bcr); ++ if (!(bcr & BCR_WPD)) { ++ bcr |= BCR_WPD; ++ pci_write_config_dword(pdev, BCR, bcr); ++ pci_read_config_dword(pdev, BCR, &bcr); ++ } ++ ++ return bcr & BCR_WPD; ++} ++ ++static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data) ++{ ++ unsigned int spi = PCI_DEVFN(13, 2); ++ struct pci_bus *bus = data; ++ u32 bcr; ++ ++ pci_bus_read_config_dword(bus, spi, BCR, &bcr); ++ if (!(bcr & BCR_WPD)) { ++ bcr |= BCR_WPD; ++ pci_bus_write_config_dword(bus, spi, BCR, bcr); ++ pci_bus_read_config_dword(bus, spi, BCR, &bcr); ++ } ++ ++ return bcr & BCR_WPD; ++} ++ + static int lpc_ich_init_spi(struct pci_dev *dev) + { + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + struct resource *res = &intel_spi_res[0]; + struct intel_spi_boardinfo *info; +- u32 spi_base, rcba, bcr; ++ u32 spi_base, rcba; + + info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); + if (!info) +@@ -1102,6 +1149,8 @@ static int lpc_ich_init_spi(struct pci_dev *dev) + if (spi_base & SPIBASE_BYT_EN) { + res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); + res->end = res->start + SPIBASE_BYT_SZ - 1; ++ ++ info->set_writeable = lpc_ich_byt_set_writeable; + } + break; + +@@ -1112,8 +1161,8 @@ static int lpc_ich_init_spi(struct pci_dev *dev) + res->start = spi_base + SPIBASE_LPT; + res->end = res->start + SPIBASE_LPT_SZ - 1; + +- pci_read_config_dword(dev, BCR, &bcr); +- info->writeable = !!(bcr & BCR_WPD); ++ info->set_writeable = lpc_ich_lpt_set_writeable; ++ info->data = dev; + } + break; + +@@ -1134,8 +1183,8 @@ static int lpc_ich_init_spi(struct pci_dev *dev) + res->start = spi_base & 0xfffffff0; + res->end = res->start + SPIBASE_APL_SZ - 1; + +- pci_bus_read_config_dword(bus, spi, BCR, &bcr); +- info->writeable = !!(bcr & BCR_WPD); ++ info->set_writeable = lpc_ich_bxt_set_writeable; ++ info->data = bus; + } + + pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); +diff --git a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c +index 555fe55d14ae..8a3c1f3c2d2e 100644 +--- a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c ++++ b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c +@@ -16,12 +16,30 @@ + #define BCR 0xdc + #define BCR_WPD BIT(0) + ++static bool intel_spi_pci_set_writeable(void __iomem *base, void *data) ++{ ++ struct pci_dev *pdev = data; ++ u32 bcr; ++ ++ /* Try to make the chip read/write */ ++ pci_read_config_dword(pdev, BCR, &bcr); ++ if (!(bcr & BCR_WPD)) { ++ bcr |= BCR_WPD; ++ pci_write_config_dword(pdev, BCR, bcr); ++ pci_read_config_dword(pdev, BCR, &bcr); ++ } ++ ++ return bcr & BCR_WPD; ++} ++ + static const struct intel_spi_boardinfo bxt_info = { + .type = INTEL_SPI_BXT, ++ .set_writeable = intel_spi_pci_set_writeable, + }; + + static const struct intel_spi_boardinfo cnl_info = { + .type = INTEL_SPI_CNL, ++ .set_writeable = intel_spi_pci_set_writeable, + }; + + static int intel_spi_pci_probe(struct pci_dev *pdev, +@@ -29,7 +47,6 @@ static int intel_spi_pci_probe(struct pci_dev *pdev, + { + struct intel_spi_boardinfo *info; + struct intel_spi *ispi; +- u32 bcr; + int ret; + + ret = pcim_enable_device(pdev); +@@ -41,15 +58,7 @@ static int intel_spi_pci_probe(struct pci_dev *pdev, + if (!info) + return -ENOMEM; + +- /* Try to make the chip read/write */ +- pci_read_config_dword(pdev, BCR, &bcr); +- if (!(bcr & BCR_WPD)) { +- bcr |= BCR_WPD; +- pci_write_config_dword(pdev, BCR, bcr); +- pci_read_config_dword(pdev, BCR, &bcr); +- } +- info->writeable = !!(bcr & BCR_WPD); +- ++ info->data = pdev; + ispi = intel_spi_probe(&pdev->dev, &pdev->resource[0], info); + if (IS_ERR(ispi)) + return PTR_ERR(ispi); +diff --git a/drivers/mtd/spi-nor/controllers/intel-spi.c b/drivers/mtd/spi-nor/controllers/intel-spi.c +index b4b0affd16c8..65f41c0781bf 100644 +--- a/drivers/mtd/spi-nor/controllers/intel-spi.c ++++ b/drivers/mtd/spi-nor/controllers/intel-spi.c +@@ -132,7 +132,6 @@ + * @sregs: Start of software sequencer registers + * @nregions: Maximum number of regions + * @pr_num: Maximum number of protected range registers +- * @writeable: Is the chip writeable + * @locked: Is SPI setting locked + * @swseq_reg: Use SW sequencer in register reads/writes + * @swseq_erase: Use SW sequencer in erase operation +@@ -150,7 +149,6 @@ struct intel_spi { + void __iomem *sregs; + size_t nregions; + size_t pr_num; +- bool writeable; + bool locked; + bool swseq_reg; + bool swseq_erase; +@@ -305,6 +303,14 @@ static int intel_spi_wait_sw_busy(struct intel_spi *ispi) + INTEL_SPI_TIMEOUT * 1000); + } + ++static bool intel_spi_set_writeable(struct intel_spi *ispi) ++{ ++ if (!ispi->info->set_writeable) ++ return false; ++ ++ return ispi->info->set_writeable(ispi->base, ispi->info->data); ++} ++ + static int intel_spi_init(struct intel_spi *ispi) + { + u32 opmenu0, opmenu1, lvscc, uvscc, val; +@@ -317,19 +323,6 @@ static int intel_spi_init(struct intel_spi *ispi) + ispi->nregions = BYT_FREG_NUM; + ispi->pr_num = BYT_PR_NUM; + ispi->swseq_reg = true; +- +- if (writeable) { +- /* Disable write protection */ +- val = readl(ispi->base + BYT_BCR); +- if (!(val & BYT_BCR_WPD)) { +- val |= BYT_BCR_WPD; +- writel(val, ispi->base + BYT_BCR); +- val = readl(ispi->base + BYT_BCR); +- } +- +- ispi->writeable = !!(val & BYT_BCR_WPD); +- } +- + break; + + case INTEL_SPI_LPT: +@@ -359,6 +352,12 @@ static int intel_spi_init(struct intel_spi *ispi) + return -EINVAL; + } + ++ /* Try to disable write protection if user asked to do so */ ++ if (writeable && !intel_spi_set_writeable(ispi)) { ++ dev_warn(ispi->dev, "can't disable chip write protection\n"); ++ writeable = false; ++ } ++ + /* Disable #SMI generation from HW sequencer */ + val = readl(ispi->base + HSFSTS_CTL); + val &= ~HSFSTS_CTL_FSMIE; +@@ -885,9 +884,12 @@ static void intel_spi_fill_partition(struct intel_spi *ispi, + /* + * If any of the regions have protection bits set, make the + * whole partition read-only to be on the safe side. ++ * ++ * Also if the user did not ask the chip to be writeable ++ * mask the bit too. + */ +- if (intel_spi_is_protected(ispi, base, limit)) +- ispi->writeable = false; ++ if (!writeable || intel_spi_is_protected(ispi, base, limit)) ++ part->mask_flags |= MTD_WRITEABLE; + + end = (limit << 12) + 4096; + if (end > part->size) +@@ -928,7 +930,6 @@ struct intel_spi *intel_spi_probe(struct device *dev, + + ispi->dev = dev; + ispi->info = info; +- ispi->writeable = info->writeable; + + ret = intel_spi_init(ispi); + if (ret) +@@ -946,10 +947,6 @@ struct intel_spi *intel_spi_probe(struct device *dev, + + intel_spi_fill_partition(ispi, &part); + +- /* Prevent writes if not explicitly enabled */ +- if (!ispi->writeable || !writeable) +- ispi->nor.mtd.flags &= ~MTD_WRITEABLE; +- + ret = mtd_device_register(&ispi->nor.mtd, &part, 1); + if (ret) + return ERR_PTR(ret); +diff --git a/include/linux/platform_data/intel-spi.h b/include/linux/platform_data/intel-spi.h +index 7f53a5c6f35e..7dda3f690465 100644 +--- a/include/linux/platform_data/intel-spi.h ++++ b/include/linux/platform_data/intel-spi.h +@@ -19,11 +19,13 @@ enum intel_spi_type { + /** + * struct intel_spi_boardinfo - Board specific data for Intel SPI driver + * @type: Type which this controller is compatible with +- * @writeable: The chip is writeable ++ * @set_writeable: Try to make the chip writeable (optional) ++ * @data: Data to be passed to @set_writeable can be %NULL + */ + struct intel_spi_boardinfo { + enum intel_spi_type type; +- bool writeable; ++ bool (*set_writeable)(void __iomem *base, void *data); ++ void *data; + }; + + #endif /* INTEL_SPI_PDATA_H */ +-- +2.35.1 + diff --git a/queue-5.10/series b/queue-5.10/series index b55797194e5..e1cb82e7f69 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -21,3 +21,11 @@ drm-imx-imx-tve-fix-return-type-of-imx_tve_connector.patch btrfs-remove-pointless-and-double-ulist-frees-in-err.patch bluetooth-l2cap-fix-l2cap_global_chan_by_psm.patch asoc-codecs-jz4725b-fix-spelling-mistake-sourc-sourc.patch +alsa-hda-realtek-fix-speakers-and-micmute-on-hp-855-.patch +mtd-spi-nor-intel-spi-disable-write-protection-only-.patch +spi-intel-use-correct-mask-for-flash-and-protected-r.patch +mmc-sdhci-esdhc-imx-use-the-correct-host-caps-for-mm.patch +drm-amd-pm-support-power-source-switch-on-sienna-cic.patch +drm-amd-pm-read-bif-strap-also-for-baco-check.patch +drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch +drm-amdgpu-disable-baco-on-special-beige_goby-card.patch diff --git a/queue-5.10/spi-intel-use-correct-mask-for-flash-and-protected-r.patch b/queue-5.10/spi-intel-use-correct-mask-for-flash-and-protected-r.patch new file mode 100644 index 00000000000..3387aaa7042 --- /dev/null +++ b/queue-5.10/spi-intel-use-correct-mask-for-flash-and-protected-r.patch @@ -0,0 +1,50 @@ +From d10a04980ad10c9a8e18eb74d9a3a2f454bb5c4d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Oct 2022 09:28:00 +0300 +Subject: spi: intel: Use correct mask for flash and protected regions + +From: Mika Westerberg + +[ Upstream commit 92a66cbf6b30eda5719fbdfb24cd15fb341bba32 ] + +The flash and protected region mask is actually 0x7fff (30:16 and 14:0) +and not 0x3fff so fix this accordingly. While there use GENMASK() instead. + +Cc: stable@vger.kernel.org +Signed-off-by: Mika Westerberg +Link: https://lore.kernel.org/r/20221025062800.22357-1-mika.westerberg@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/mtd/spi-nor/controllers/intel-spi.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/mtd/spi-nor/controllers/intel-spi.c b/drivers/mtd/spi-nor/controllers/intel-spi.c +index 65f41c0781bf..6c802db6b4af 100644 +--- a/drivers/mtd/spi-nor/controllers/intel-spi.c ++++ b/drivers/mtd/spi-nor/controllers/intel-spi.c +@@ -53,17 +53,17 @@ + #define FRACC 0x50 + + #define FREG(n) (0x54 + ((n) * 4)) +-#define FREG_BASE_MASK 0x3fff ++#define FREG_BASE_MASK GENMASK(14, 0) + #define FREG_LIMIT_SHIFT 16 +-#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT) ++#define FREG_LIMIT_MASK GENMASK(30, 16) + + /* Offset is from @ispi->pregs */ + #define PR(n) ((n) * 4) + #define PR_WPE BIT(31) + #define PR_LIMIT_SHIFT 16 +-#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT) ++#define PR_LIMIT_MASK GENMASK(30, 16) + #define PR_RPE BIT(15) +-#define PR_BASE_MASK 0x3fff ++#define PR_BASE_MASK GENMASK(14, 0) + + /* Offsets are from @ispi->sregs */ + #define SSFSTS_CTL 0x00 +-- +2.35.1 +