From: Michal Simek Date: Mon, 8 Feb 2016 08:34:53 +0000 (+0100) Subject: ARM64: zynqmp: Read RAM information from DT X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=f17b4cbe81593518f15d96dfd4dc19b04a1b9a9d;p=thirdparty%2Fu-boot.git ARM64: zynqmp: Read RAM information from DT Read information about memory from DT. This patch simplify life with synchronization between DT and board files. zynqmp-mini-nand, zynqmp-mini-qspi are not converted because they need specific settings which needs to be tested. dram_init() only needs maximum RAM size below 4GB that's why please sort banks in memory node. dram_init_banksize() copies memory setup to bi_dram[]. This will avoid reading information from DT twice. Memory test start/end were changed to DDR location to let memtest still compiled. Signed-off-by: Michal Simek --- diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 85b3527244b..303b132c9a7 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -62,12 +62,129 @@ int board_early_init_r(void) return 0; } +#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +/* + * fdt_get_reg - Fill buffer by information from DT + */ +static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, + const u32 *cell, int n) +{ + int i = 0, b, banks; + int address_cells = fdt_address_cells(fdt, nodeoffset); + int size_cells = fdt_size_cells(fdt, nodeoffset); + char *p = buf; + phys_addr_t val; + phys_size_t vals; + + debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", + __func__, address_cells, size_cells, buf, cell); + + /* Check memory bank setup */ + banks = n % (address_cells + size_cells); + if (banks) + panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n", + n, address_cells, size_cells); + + banks = n / (address_cells + size_cells); + + for (b = 0; b < banks; b++) { + debug("%s: Bank #%d:\n", __func__, b); + if (address_cells == 2) { + val = cell[i + 1]; + val <<= 32; + val |= cell[i]; + val = fdt64_to_cpu(val); + debug("%s: addr64=%llx, ptr=%p, cell=%p\n", + __func__, val, p, &cell[i]); + *(phys_addr_t *)p = val; + } else { + debug("%s: addr32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_addr_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_addr_t); + i += address_cells; + + debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i, + sizeof(phys_addr_t)); + + if (size_cells == 2) { + vals = cell[i + 1]; + vals <<= 32; + vals |= cell[i]; + vals = fdt64_to_cpu(vals); + + debug("%s: size64=%llx, ptr=%p, cell=%p\n", + __func__, vals, p, &cell[i]); + *(phys_size_t *)p = vals; + } else { + debug("%s: size32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_size_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_size_t); + i += size_cells; + + debug("%s: ps=%p, i=%x, size=%zu\n", + __func__, p, i, sizeof(phys_size_t)); + } + + /* Return the first address size */ + return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t)); +} + +#define FDT_REG_SIZE sizeof(u32) +/* Temp location for sharing data for storing */ +u8 tmp[CONFIG_NR_DRAM_BANKS * 16]; /* Up to 64-bit address + 64-bit size */ + +void dram_init_banksize(void) +{ + int bank; + + memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp)); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + debug("Bank #%d: start %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].start); + debug("Bank #%d: size %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].size); + } +} + +int dram_init(void) +{ + int node, len; + const void *blob = gd->fdt_blob; + const u32 *cell; + + /* find or create "/memory" node. */ + node = fdt_subnode_offset(blob, 0, "memory"); + if (node < 0) { + printf("%s: Can't get memory node\n", __func__); + return node; + } + + /* Get pointer to cells and lenght of it */ + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) { + printf("%s: Can't get reg property\n", __func__); + return -1; + } + + gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE); + + debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size); + + return 0; +} +#else int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } +#endif void reset_cpu(ulong addr) { diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 2c00e79294d..26b2a4a55c8 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -26,8 +26,11 @@ #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE +#ifndef CONFIG_NR_DRAM_BANKS +# define CONFIG_NR_DRAM_BANKS 2 +#endif +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END 1000 /* Have release address at the end of 256MB for now */ #define CPU_RELEASE_ADDR 0xFFFFFF0 @@ -41,7 +44,7 @@ #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.Xilinx_ZynqMP" /* Text base on 16MB for now - 0 doesn't work */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index d67bed77712..c90723a30cf 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -23,11 +23,6 @@ #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 - #define COUNTER_FREQUENCY 4000000 #define CONFIG_KERNEL_FDT_OFST_SIZE \ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 554dd7acc19..8b777321764 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -70,6 +70,7 @@ #define CONFIG_CMD_MEMORY #define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */ +#undef CONFIG_NR_DRAM_BANKS #define CONFIG_NR_DRAM_BANKS 1 #if defined(CONFIG_MINI_QSPI) diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h index 55b36cb5c06..7aa99368815 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h @@ -19,11 +19,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1" -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - #define CONFIG_KERNEL_FDT_OFST_SIZE \ "kernel_offset=0x400000\0" \ "fdt_offset=0x2400000\0" \ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h index fd17a0c848e..2727dc6e070 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h @@ -16,11 +16,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2" -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - #define CONFIG_KERNEL_FDT_OFST_SIZE \ "kernel_offset=0x400000\0" \ "fdt_offset=0x2400000\0" \ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h index 4d4d26f6db6..d9409bad655 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h @@ -18,11 +18,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5" -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - #define CONFIG_KERNEL_FDT_OFST_SIZE \ "kernel_offset=0x400000\0" \ "fdt_offset=0x2400000\0" \ diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 051f89d4cc6..4f580207bb3 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -44,11 +44,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102" -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - #define CONFIG_KERNEL_FDT_OFST_SIZE \ "kernel_offset=0x180000\0" \ "fdt_offset=0x100000\0" \