From: Greg Kroah-Hartman Date: Mon, 21 Aug 2023 16:46:25 +0000 (+0200) Subject: 6.1-stable patches X-Git-Tag: v6.4.12~28 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=f478a7b892955c873c14ee53f6d8e6561f3b3e65;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: arm64-ptrace-ensure-that-sme-is-set-up-for-target-when-writing-ssve-state.patch drm-amd-pm-skip-the-rlc-stop-when-s0i3-suspend-for-smu-v13.0.4-11.patch drm-amdgpu-keep-irq-count-in-amdgpu_irq_disable_all.patch --- diff --git a/queue-6.1/arm64-ptrace-ensure-that-sme-is-set-up-for-target-when-writing-ssve-state.patch b/queue-6.1/arm64-ptrace-ensure-that-sme-is-set-up-for-target-when-writing-ssve-state.patch new file mode 100644 index 00000000000..463c40c3c7a --- /dev/null +++ b/queue-6.1/arm64-ptrace-ensure-that-sme-is-set-up-for-target-when-writing-ssve-state.patch @@ -0,0 +1,116 @@ +From 5d0a8d2fba50e9c07cde4aad7fba28c008b07a5b Mon Sep 17 00:00:00 2001 +From: Mark Brown +Date: Thu, 10 Aug 2023 12:28:19 +0100 +Subject: arm64/ptrace: Ensure that SME is set up for target when writing SSVE state + +From: Mark Brown + +commit 5d0a8d2fba50e9c07cde4aad7fba28c008b07a5b upstream. + +When we use NT_ARM_SSVE to either enable streaming mode or change the +vector length for a process we do not currently do anything to ensure that +there is storage allocated for the SME specific register state. If the +task had not previously used SME or we changed the vector length then +the task will not have had TIF_SME set or backing storage for ZA/ZT +allocated, resulting in inconsistent register sizes when saving state +and spurious traps which flush the newly set register state. + +We should set TIF_SME to disable traps and ensure that storage is +allocated for ZA and ZT if it is not already allocated. This requires +modifying sme_alloc() to make the flush of any existing register state +optional so we don't disturb existing state for ZA and ZT. + +Fixes: e12310a0d30f ("arm64/sme: Implement ptrace support for streaming mode SVE registers") +Reported-by: David Spickett +Signed-off-by: Mark Brown +Cc: # 5.19.x +Link: https://lore.kernel.org/r/20230810-arm64-fix-ptrace-race-v1-1-a5361fad2bd6@kernel.org +Signed-off-by: Catalin Marinas +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/fpsimd.h | 4 ++-- + arch/arm64/kernel/fpsimd.c | 6 +++--- + arch/arm64/kernel/ptrace.c | 9 ++++++++- + arch/arm64/kernel/signal.c | 2 +- + 4 files changed, 14 insertions(+), 7 deletions(-) + +--- a/arch/arm64/include/asm/fpsimd.h ++++ b/arch/arm64/include/asm/fpsimd.h +@@ -339,7 +339,7 @@ static inline int sme_max_virtualisable_ + return vec_max_virtualisable_vl(ARM64_VEC_SME); + } + +-extern void sme_alloc(struct task_struct *task); ++extern void sme_alloc(struct task_struct *task, bool flush); + extern unsigned int sme_get_vl(void); + extern int sme_set_current_vl(unsigned long arg); + extern int sme_get_current_vl(void); +@@ -365,7 +365,7 @@ static inline void sme_smstart_sm(void) + static inline void sme_smstop_sm(void) { } + static inline void sme_smstop(void) { } + +-static inline void sme_alloc(struct task_struct *task) { } ++static inline void sme_alloc(struct task_struct *task, bool flush) { } + static inline void sme_setup(void) { } + static inline unsigned int sme_get_vl(void) { return 0; } + static inline int sme_max_vl(void) { return 0; } +--- a/arch/arm64/kernel/fpsimd.c ++++ b/arch/arm64/kernel/fpsimd.c +@@ -1239,9 +1239,9 @@ void fpsimd_release_task(struct task_str + * the interest of testability and predictability, the architecture + * guarantees that when ZA is enabled it will be zeroed. + */ +-void sme_alloc(struct task_struct *task) ++void sme_alloc(struct task_struct *task, bool flush) + { +- if (task->thread.za_state) { ++ if (task->thread.za_state && flush) { + memset(task->thread.za_state, 0, za_state_size(task)); + return; + } +@@ -1460,7 +1460,7 @@ void do_sme_acc(unsigned long esr, struc + } + + sve_alloc(current, false); +- sme_alloc(current); ++ sme_alloc(current, true); + if (!current->thread.sve_state || !current->thread.za_state) { + force_sig(SIGKILL); + return; +--- a/arch/arm64/kernel/ptrace.c ++++ b/arch/arm64/kernel/ptrace.c +@@ -886,6 +886,13 @@ static int sve_set_common(struct task_st + break; + case ARM64_VEC_SME: + target->thread.svcr |= SVCR_SM_MASK; ++ ++ /* ++ * Disable traps and ensure there is SME storage but ++ * preserve any currently set values in ZA/ZT. ++ */ ++ sme_alloc(target, false); ++ set_tsk_thread_flag(target, TIF_SME); + break; + default: + WARN_ON_ONCE(1); +@@ -1107,7 +1114,7 @@ static int za_set(struct task_struct *ta + } + + /* Allocate/reinit ZA storage */ +- sme_alloc(target); ++ sme_alloc(target, true); + if (!target->thread.za_state) { + ret = -ENOMEM; + goto out; +--- a/arch/arm64/kernel/signal.c ++++ b/arch/arm64/kernel/signal.c +@@ -430,7 +430,7 @@ static int restore_za_context(struct use + fpsimd_flush_task_state(current); + /* From now, fpsimd_thread_switch() won't touch thread.sve_state */ + +- sme_alloc(current); ++ sme_alloc(current, true); + if (!current->thread.za_state) { + current->thread.svcr &= ~SVCR_ZA_MASK; + clear_thread_flag(TIF_SME); diff --git a/queue-6.1/drm-amd-pm-skip-the-rlc-stop-when-s0i3-suspend-for-smu-v13.0.4-11.patch b/queue-6.1/drm-amd-pm-skip-the-rlc-stop-when-s0i3-suspend-for-smu-v13.0.4-11.patch new file mode 100644 index 00000000000..999b45b6a50 --- /dev/null +++ b/queue-6.1/drm-amd-pm-skip-the-rlc-stop-when-s0i3-suspend-for-smu-v13.0.4-11.patch @@ -0,0 +1,34 @@ +From 730d44e1fa306a20746ad4a85da550662aed9daa Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Thu, 27 Jul 2023 09:59:45 +0800 +Subject: drm/amd/pm: skip the RLC stop when S0i3 suspend for SMU v13.0.4/11 + +From: Tim Huang + +commit 730d44e1fa306a20746ad4a85da550662aed9daa upstream. + +For SMU v13.0.4/11, driver does not need to stop RLC for S0i3, +the firmwares will handle that properly. + +Signed-off-by: Tim Huang +Reviewed-by: Mario Limonciello +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -1562,9 +1562,9 @@ static int smu_disable_dpms(struct smu_c + + /* + * For SMU 13.0.4/11, PMFW will handle the features disablement properly +- * for gpu reset case. Driver involvement is unnecessary. ++ * for gpu reset and S0i3 cases. Driver involvement is unnecessary. + */ +- if (amdgpu_in_reset(adev)) { ++ if (amdgpu_in_reset(adev) || adev->in_s0ix) { + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 4): + case IP_VERSION(13, 0, 11): diff --git a/queue-6.1/drm-amdgpu-keep-irq-count-in-amdgpu_irq_disable_all.patch b/queue-6.1/drm-amdgpu-keep-irq-count-in-amdgpu_irq_disable_all.patch new file mode 100644 index 00000000000..38d33e3d0e7 --- /dev/null +++ b/queue-6.1/drm-amdgpu-keep-irq-count-in-amdgpu_irq_disable_all.patch @@ -0,0 +1,34 @@ +From 8ffd6f0442674f32c048ec8dffdbc5ec67829beb Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Thu, 25 May 2023 17:24:31 +0800 +Subject: drm/amdgpu: keep irq count in amdgpu_irq_disable_all +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Guchun Chen + +commit 8ffd6f0442674f32c048ec8dffdbc5ec67829beb upstream. + +This can clean up all irq warnings because of unbalanced +amdgpu_irq_get/put when unplugging/unbinding device, and leave +irq count decrease in each ip fini function. + +Signed-off-by: Guchun Chen +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +@@ -160,7 +160,6 @@ void amdgpu_irq_disable_all(struct amdgp + continue; + + for (k = 0; k < src->num_types; ++k) { +- atomic_set(&src->enabled_types[k], 0); + r = src->funcs->set(adev, src, k, + AMDGPU_IRQ_STATE_DISABLE); + if (r) diff --git a/queue-6.1/series b/queue-6.1/series index 38380da3990..2374276320f 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -185,3 +185,6 @@ x86-srso-disable-the-mitigation-on-unaffected-configurations.patch x86-retpoline-kprobes-fix-position-of-thunk-sections-with-config_lto_clang.patch objtool-x86-fixup-frame-pointer-vs-rethunk.patch x86-srso-correct-the-mitigation-status-when-smt-is-disabled.patch +arm64-ptrace-ensure-that-sme-is-set-up-for-target-when-writing-ssve-state.patch +drm-amd-pm-skip-the-rlc-stop-when-s0i3-suspend-for-smu-v13.0.4-11.patch +drm-amdgpu-keep-irq-count-in-amdgpu_irq_disable_all.patch